2 * Kernel execution entry point code.
4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 * Initial PowerPC version.
6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 * Low-level exception handers, MMU support, and rewrite.
10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 * PowerPC 8xx modifications.
12 * Copyright (c) 1998-1999 TiVo, Inc.
13 * PowerPC 403GCX modifications.
14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 * PowerPC 403GCX/405GP modifications.
16 * Copyright 2000 MontaVista Software Inc.
17 * PPC405 modifications
18 * PowerPC 403GCX/405GP modifications.
19 * Author: MontaVista Software, Inc.
20 * frank_rowand@mvista.com or source@mvista.com
21 * debbie_chu@mvista.com
22 * Copyright 2002-2004 MontaVista Software, Inc.
23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
24 * Copyright 2004 Freescale Semiconductor, Inc
25 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
27 * This program is free software; you can redistribute it and/or modify it
28 * under the terms of the GNU General Public License as published by the
29 * Free Software Foundation; either version 2 of the License, or (at your
30 * option) any later version.
33 #include <linux/threads.h>
34 #include <asm/processor.h>
37 #include <asm/pgtable.h>
38 #include <asm/cputable.h>
39 #include <asm/thread_info.h>
40 #include <asm/ppc_asm.h>
41 #include <asm/asm-offsets.h>
42 #include "head_booke.h"
44 /* As with the other PowerPC ports, it is expected that when code
45 * execution begins here, the following registers contain valid, yet
46 * optional, information:
48 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
49 * r4 - Starting address of the init RAM disk
50 * r5 - Ending address of the init RAM disk
51 * r6 - Start of kernel command line string (e.g. "mem=128")
52 * r7 - End of kernel command line string
55 .section .text.head, "ax"
59 * Reserve a word at a fixed location to store the address
64 * Save parameters we are passed
71 li r25,0 /* phys kernel start (low) */
72 li r24,0 /* CPU number */
73 li r23,0 /* phys kernel start (high) */
75 /* We try to not make any assumptions about how the boot loader
76 * setup or used the TLBs. We invalidate all mappings from the
77 * boot loader and load a single entry in TLB1[0] to map the
78 * first 64M of kernel memory. Any boot info passed from the
79 * bootloader needs to live in this first 64M.
81 * Requirement on bootloader:
82 * - The page we're executing in needs to reside in TLB1 and
83 * have IPROT=1. If not an invalidate broadcast could
84 * evict the entry we're currently executing in.
86 * r3 = Index of TLB1 were executing in
87 * r4 = Current MSR[IS]
88 * r5 = Index of TLB1 temp mapping
90 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
94 /* 1. Find the index of the entry we're executing in */
95 bl invstr /* Find our address */
96 invstr: mflr r6 /* Make it accessible */
98 rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
103 tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
106 andis. r7,r7,MAS1_VALID@h
112 tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
114 andis. r7,r7,MAS1_VALID@h
120 tlbsx 0,r6 /* Fall through, we had to match */
124 rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
126 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
127 oris r7,r7,MAS1_IPROT@h
131 /* 2. Invalidate all entries except the entry we're executing in */
132 mfspr r9,SPRN_TLB1CFG
134 li r6,0 /* Set Entry counter to 0 */
135 1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
136 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
140 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
142 beq skpinv /* Dont update the current execution TLB */
146 skpinv: addi r6,r6,1 /* Increment */
147 cmpw r6,r9 /* Are we done? */
148 bne 1b /* If not, repeat */
150 /* Invalidate TLB0 */
156 /* Invalidate TLB1 */
164 /* 3. Setup a temp mapping and jump to it */
165 andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
167 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
168 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
172 /* grab and fixup the RPN */
173 mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
174 rlwinm r6,r6,25,27,30
177 slw r6,r8,r6 /* convert to mask */
179 bl 1f /* Find our address */
183 #ifdef CONFIG_PHYS_64BIT
191 ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
193 /* Just modify the entry ID and EPN for the temp mapping */
194 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
195 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
197 xori r6,r4,1 /* Setup TMP mapping in the other Address space */
199 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
200 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
203 li r7,0 /* temp EPN = 0 */
210 slwi r6,r6,5 /* setup new context with other address space */
211 bl 1f /* Find our address */
219 /* 4. Clear out PIDs & Search info */
228 /* 5. Invalidate mapping we started in */
229 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
230 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
234 rlwinm r6,r6,0,2,0 /* clear IPROT */
237 /* Invalidate TLB1 */
245 /* 6. Setup KERNELBASE mapping in TLB1[0] */
246 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
248 lis r6,(MAS1_VALID|MAS1_IPROT)@h
249 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
253 ori r6,r6,PAGE_OFFSET@l
259 /* 7. Jump to KERNELBASE mapping */
261 ori r6,r6,KERNELBASE@l
264 ori r7,r7,MSR_KERNEL@l
265 bl 1f /* Find our address */
271 rfi /* start execution out of TLB1[0] entry */
273 /* 8. Clear out the temp mapping */
274 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
275 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
279 rlwinm r8,r8,0,2,0 /* clear IPROT */
282 /* Invalidate TLB1 */
290 /* Establish the interrupt vector offsets */
291 SET_IVOR(0, CriticalInput);
292 SET_IVOR(1, MachineCheck);
293 SET_IVOR(2, DataStorage);
294 SET_IVOR(3, InstructionStorage);
295 SET_IVOR(4, ExternalInput);
296 SET_IVOR(5, Alignment);
297 SET_IVOR(6, Program);
298 SET_IVOR(7, FloatingPointUnavailable);
299 SET_IVOR(8, SystemCall);
300 SET_IVOR(9, AuxillaryProcessorUnavailable);
301 SET_IVOR(10, Decrementer);
302 SET_IVOR(11, FixedIntervalTimer);
303 SET_IVOR(12, WatchdogTimer);
304 SET_IVOR(13, DataTLBError);
305 SET_IVOR(14, InstructionTLBError);
306 SET_IVOR(15, DebugDebug);
307 #if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC)
308 SET_IVOR(15, DebugCrit);
310 SET_IVOR(32, SPEUnavailable);
311 SET_IVOR(33, SPEFloatingPointData);
312 SET_IVOR(34, SPEFloatingPointRound);
314 SET_IVOR(35, PerformanceMonitor);
316 #ifdef CONFIG_PPC_E500MC
317 SET_IVOR(36, Doorbell);
320 /* Establish the interrupt vector base */
321 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
324 /* Setup the defaults for TLB entries */
325 li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
327 oris r2,r2,MAS4_TLBSELD(1)@h
334 oris r2,r2,HID0_DOZE@h
338 /* enable dedicated debug exception handling resources (Debug APU) */
340 ori r2,r2,HID0_DAPUEN@l
344 #if !defined(CONFIG_BDI_SWITCH)
346 * The Abatron BDI JTAG debugger does not tolerate others
347 * mucking with the debug registers.
352 /* clear any residual debug events */
358 * This is where the main kernel code starts.
363 ori r2,r2,init_task@l
365 /* ptr to current thread */
366 addi r4,r2,THREAD /* init task's THREAD */
370 lis r1,init_thread_union@h
371 ori r1,r1,init_thread_union@l
373 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
377 #ifdef CONFIG_RELOCATABLE
378 lis r3,kernstart_addr@ha
379 la r3,kernstart_addr@l(r3)
380 #ifdef CONFIG_PHYS_64BIT
388 mfspr r3,SPRN_TLB1CFG
390 lis r4,num_tlbcam_entries@ha
391 stw r3,num_tlbcam_entries@l(r4)
393 * Decide what sort of machine this is and initialize the MMU.
403 /* Setup PTE pointers for the Abatron bdiGDB */
404 lis r6, swapper_pg_dir@h
405 ori r6, r6, swapper_pg_dir@l
406 lis r5, abatron_pteptrs@h
407 ori r5, r5, abatron_pteptrs@l
409 ori r4, r4, KERNELBASE@l
410 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
414 lis r4,start_kernel@h
415 ori r4,r4,start_kernel@l
417 ori r3,r3,MSR_KERNEL@l
420 rfi /* change context and jump to start_kernel */
422 /* Macros to hide the PTE size differences
424 * FIND_PTE -- walks the page tables given EA & pgdir pointer
426 * r11 -- PGDIR pointer
428 * label 2: is the bailout case
430 * if we find the pte (fall through):
431 * r11 is low pte word
432 * r12 is pointer to the pte
434 #ifdef CONFIG_PTE_64BIT
435 #define PTE_FLAGS_OFFSET 4
437 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
438 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
439 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
440 beq 2f; /* Bail if no table */ \
441 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
442 lwz r11, 4(r12); /* Get pte entry */
444 #define PTE_FLAGS_OFFSET 0
446 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
447 lwz r11, 0(r11); /* Get L1 entry */ \
448 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
449 beq 2f; /* Bail if no table */ \
450 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
451 lwz r11, 0(r12); /* Get Linux PTE */
455 * Interrupt vector entry code
457 * The Book E MMUs are always on so we don't need to handle
458 * interrupts in real mode as with previous PPC processors. In
459 * this case we handle interrupts in the kernel virtual address
462 * Interrupt vectors are dynamically placed relative to the
463 * interrupt prefix as determined by the address of interrupt_base.
464 * The interrupt vectors offsets are programmed using the labels
465 * for each interrupt vector entry.
467 * Interrupt vectors must be aligned on a 16 byte boundary.
468 * We align on a 32 byte cache line boundary for good measure.
472 /* Critical Input Interrupt */
473 CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
475 /* Machine Check Interrupt */
477 /* no RFMCI, MCSRRs on E200 */
478 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
480 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
483 /* Data Storage Interrupt */
484 START_EXCEPTION(DataStorage)
485 mtspr SPRN_SPRG0, r10 /* Save some working registers */
486 mtspr SPRN_SPRG1, r11
487 mtspr SPRN_SPRG4W, r12
488 mtspr SPRN_SPRG5W, r13
490 mtspr SPRN_SPRG7W, r11
493 * Check if it was a store fault, if not then bail
494 * because a user tried to access a kernel or
495 * read-protected page. Otherwise, get the
496 * offending address and handle it.
499 andis. r10, r10, ESR_ST@h
502 mfspr r10, SPRN_DEAR /* Get faulting address */
504 /* If we are faulting a kernel address, we have to use the
505 * kernel page tables.
507 lis r11, PAGE_OFFSET@h
511 /* Get the PGD for the current thread */
518 /* Are _PAGE_USER & _PAGE_RW set & _PAGE_HWWRITE not? */
519 andi. r13, r11, _PAGE_RW|_PAGE_USER|_PAGE_HWWRITE
520 cmpwi 0, r13, _PAGE_RW|_PAGE_USER
521 bne 2f /* Bail if not */
523 /* Update 'changed'. */
524 ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
525 stw r11, PTE_FLAGS_OFFSET(r12) /* Update Linux page table */
527 /* MAS2 not updated as the entry does exist in the tlb, this
528 fault taken to detect state transition (eg: COW -> DIRTY)
530 andi. r11, r11, _PAGE_HWEXEC
531 rlwimi r11, r11, 31, 27, 27 /* SX <- _PAGE_HWEXEC */
532 ori r11, r11, (MAS3_UW|MAS3_SW|MAS3_UR|MAS3_SR)@l /* set static perms */
534 /* update search PID in MAS6, AS = 0 */
539 /* find the TLB index that caused the fault. It has to be here. */
542 /* only update the perm bits, assume the RPN is fine */
544 rlwimi r12, r11, 0, 20, 31
548 /* Done...restore registers and get out of here. */
549 mfspr r11, SPRN_SPRG7R
551 mfspr r13, SPRN_SPRG5R
552 mfspr r12, SPRN_SPRG4R
553 mfspr r11, SPRN_SPRG1
554 mfspr r10, SPRN_SPRG0
555 rfi /* Force context change */
559 * The bailout. Restore registers to pre-exception conditions
560 * and call the heavyweights to help us out.
562 mfspr r11, SPRN_SPRG7R
564 mfspr r13, SPRN_SPRG5R
565 mfspr r12, SPRN_SPRG4R
566 mfspr r11, SPRN_SPRG1
567 mfspr r10, SPRN_SPRG0
570 /* Instruction Storage Interrupt */
571 INSTRUCTION_STORAGE_EXCEPTION
573 /* External Input Interrupt */
574 EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
576 /* Alignment Interrupt */
579 /* Program Interrupt */
582 /* Floating Point Unavailable Interrupt */
583 #ifdef CONFIG_PPC_FPU
584 FP_UNAVAILABLE_EXCEPTION
587 /* E200 treats 'normal' floating point instructions as FP Unavail exception */
588 EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
590 EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
594 /* System Call Interrupt */
595 START_EXCEPTION(SystemCall)
596 NORMAL_EXCEPTION_PROLOG
597 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
599 /* Auxillary Processor Unavailable Interrupt */
600 EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
602 /* Decrementer Interrupt */
603 DECREMENTER_EXCEPTION
605 /* Fixed Internal Timer Interrupt */
606 /* TODO: Add FIT support */
607 EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
609 /* Watchdog Timer Interrupt */
610 #ifdef CONFIG_BOOKE_WDT
611 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
613 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
616 /* Data TLB Error Interrupt */
617 START_EXCEPTION(DataTLBError)
618 mtspr SPRN_SPRG0, r10 /* Save some working registers */
619 mtspr SPRN_SPRG1, r11
620 mtspr SPRN_SPRG4W, r12
621 mtspr SPRN_SPRG5W, r13
623 mtspr SPRN_SPRG7W, r11
624 mfspr r10, SPRN_DEAR /* Get faulting address */
626 /* If we are faulting a kernel address, we have to use the
627 * kernel page tables.
629 lis r11, PAGE_OFFSET@h
632 lis r11, swapper_pg_dir@h
633 ori r11, r11, swapper_pg_dir@l
635 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
636 rlwinm r12,r12,0,16,1
641 /* Get the PGD for the current thread */
648 andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
649 beq 2f /* Bail if not present */
651 #ifdef CONFIG_PTE_64BIT
654 ori r11, r11, _PAGE_ACCESSED
655 stw r11, PTE_FLAGS_OFFSET(r12)
657 /* Jump to common tlb load */
660 /* The bailout. Restore registers to pre-exception conditions
661 * and call the heavyweights to help us out.
663 mfspr r11, SPRN_SPRG7R
665 mfspr r13, SPRN_SPRG5R
666 mfspr r12, SPRN_SPRG4R
667 mfspr r11, SPRN_SPRG1
668 mfspr r10, SPRN_SPRG0
671 /* Instruction TLB Error Interrupt */
673 * Nearly the same as above, except we get our
674 * information from different registers and bailout
675 * to a different point.
677 START_EXCEPTION(InstructionTLBError)
678 mtspr SPRN_SPRG0, r10 /* Save some working registers */
679 mtspr SPRN_SPRG1, r11
680 mtspr SPRN_SPRG4W, r12
681 mtspr SPRN_SPRG5W, r13
683 mtspr SPRN_SPRG7W, r11
684 mfspr r10, SPRN_SRR0 /* Get faulting address */
686 /* If we are faulting a kernel address, we have to use the
687 * kernel page tables.
689 lis r11, PAGE_OFFSET@h
692 lis r11, swapper_pg_dir@h
693 ori r11, r11, swapper_pg_dir@l
695 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
696 rlwinm r12,r12,0,16,1
701 /* Get the PGD for the current thread */
708 andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
709 beq 2f /* Bail if not present */
711 #ifdef CONFIG_PTE_64BIT
714 ori r11, r11, _PAGE_ACCESSED
715 stw r11, PTE_FLAGS_OFFSET(r12)
717 /* Jump to common TLB load point */
721 /* The bailout. Restore registers to pre-exception conditions
722 * and call the heavyweights to help us out.
724 mfspr r11, SPRN_SPRG7R
726 mfspr r13, SPRN_SPRG5R
727 mfspr r12, SPRN_SPRG4R
728 mfspr r11, SPRN_SPRG1
729 mfspr r10, SPRN_SPRG0
733 /* SPE Unavailable */
734 START_EXCEPTION(SPEUnavailable)
735 NORMAL_EXCEPTION_PROLOG
737 addi r3,r1,STACK_FRAME_OVERHEAD
738 EXC_XFER_EE_LITE(0x2010, KernelSPE)
740 EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
741 #endif /* CONFIG_SPE */
743 /* SPE Floating Point Data */
745 EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
747 EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
748 #endif /* CONFIG_SPE */
750 /* SPE Floating Point Round */
751 EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
753 /* Performance Monitor */
754 EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
756 #ifdef CONFIG_PPC_E500MC
757 EXCEPTION(0x2070, Doorbell, unknown_exception, EXC_XFER_EE)
760 /* Debug Interrupt */
761 DEBUG_DEBUG_EXCEPTION
762 #if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC)
771 * Data TLB exceptions will bail out to this point
772 * if they can't resolve the lightweight TLB fault.
775 NORMAL_EXCEPTION_PROLOG
776 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
778 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
779 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
781 EXC_XFER_EE_LITE(0x0300, handle_page_fault)
783 addi r3,r1,STACK_FRAME_OVERHEAD
784 EXC_XFER_EE_LITE(0x0300, CacheLockingException)
788 * Both the instruction and data TLB miss get to this
789 * point to load the TLB.
791 * r11 - TLB (info from Linux PTE)
792 * r12, r13 - available to use
793 * CR5 - results of addr >= PAGE_OFFSET
794 * MAS0, MAS1 - loaded with proper value when we get here
795 * MAS2, MAS3 - will need additional info from Linux PTE
796 * Upon exit, we reload everything and RFI.
800 * We set execute, because we don't have the granularity to
801 * properly set this at the page level (Linux problem).
802 * Many of these bits are software only. Bits we don't set
803 * here we (properly should) assume have the appropriate value.
807 #ifdef CONFIG_PTE_64BIT
808 rlwimi r12, r11, 26, 24, 31 /* extract ...WIMGE from pte */
810 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
817 andi. r12, r11, (_PAGE_USER | _PAGE_HWWRITE | _PAGE_HWEXEC)
818 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
820 or r12, r12, r10 /* Copy user perms into supervisor */
825 1: rlwinm r12, r11, 31, 29, 29 /* Extract _PAGE_HWWRITE into SW */
826 ori r12, r12, (MAS3_SX | MAS3_SR)
828 #ifdef CONFIG_PTE_64BIT
829 2: rlwimi r12, r13, 24, 0, 7 /* grab RPN[32:39] */
830 rlwimi r12, r11, 24, 8, 19 /* grab RPN[40:51] */
833 srwi r10, r13, 8 /* grab RPN[8:31] */
835 END_FTR_SECTION_IFSET(CPU_FTR_BIG_PHYS)
837 2: rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */
841 /* Round robin TLB1 entries assignment */
844 /* Extract TLB1CFG(NENTRY) */
845 mfspr r11, SPRN_TLB1CFG
846 andi. r11, r11, 0xfff
848 /* Extract MAS0(NV) */
849 andi. r13, r12, 0xfff
854 /* check if we need to wrap */
857 /* wrap back to first free tlbcam entry */
858 lis r13, tlbcam_index@ha
859 lwz r13, tlbcam_index@l(r13)
860 rlwimi r12, r13, 0, 20, 31
863 #endif /* CONFIG_E200 */
867 /* Done...restore registers and get out of here. */
868 mfspr r11, SPRN_SPRG7R
870 mfspr r13, SPRN_SPRG5R
871 mfspr r12, SPRN_SPRG4R
872 mfspr r11, SPRN_SPRG1
873 mfspr r10, SPRN_SPRG0
874 rfi /* Force context change */
877 /* Note that the SPE support is closely modeled after the AltiVec
878 * support. Changes to one are likely to be applicable to the
882 * Disable SPE for the task which had SPE previously,
883 * and save its SPE registers in its thread_struct.
884 * Enables SPE for use in the kernel on return.
885 * On SMP we know the SPE units are free, since we give it up every
890 mtmsr r5 /* enable use of SPE now */
893 * For SMP, we don't do lazy SPE switching because it just gets too
894 * horrendously complex, especially when a task switches from one CPU
895 * to another. Instead we call giveup_spe in switch_to.
898 lis r3,last_task_used_spe@ha
899 lwz r4,last_task_used_spe@l(r3)
902 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
903 SAVE_32EVRS(0,r10,r4)
904 evxor evr10, evr10, evr10 /* clear out evr10 */
905 evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
907 evstddx evr10, r4, r5 /* save off accumulator */
909 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
911 andc r4,r4,r10 /* disable SPE for previous task */
912 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
914 #endif /* !CONFIG_SMP */
915 /* enable use of SPE after return */
917 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
920 stw r4,THREAD_USED_SPE(r5)
923 REST_32EVRS(0,r10,r5)
926 stw r4,last_task_used_spe@l(r3)
927 #endif /* !CONFIG_SMP */
928 /* restore registers and return */
929 2: REST_4GPRS(3, r11)
944 * SPE unavailable trap from kernel - print a message, but let
945 * the task use SPE in the kernel until it returns to user mode.
950 stw r3,_MSR(r1) /* enable use of SPE after return */
953 mr r4,r2 /* current */
957 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
960 #endif /* CONFIG_SPE */
967 * extern void loadcam_entry(unsigned int index)
969 * Load TLBCAM[index] entry in to the L2 CAM MMU
971 _GLOBAL(loadcam_entry)
989 * extern void giveup_altivec(struct task_struct *prev)
991 * The e500 core does not have an AltiVec unit.
993 _GLOBAL(giveup_altivec)
998 * extern void giveup_spe(struct task_struct *prev)
1003 oris r5,r5,MSR_SPE@h
1004 mtmsr r5 /* enable use of SPE now */
1007 beqlr- /* if no previous owner, done */
1008 addi r3,r3,THREAD /* want THREAD of task */
1011 SAVE_32EVRS(0, r4, r3)
1012 evxor evr6, evr6, evr6 /* clear out evr6 */
1013 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
1015 evstddx evr6, r4, r3 /* save off accumulator */
1016 mfspr r6,SPRN_SPEFSCR
1017 stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */
1019 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1021 andc r4,r4,r3 /* disable SPE for previous task */
1022 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1026 lis r4,last_task_used_spe@ha
1027 stw r5,last_task_used_spe@l(r4)
1028 #endif /* !CONFIG_SMP */
1030 #endif /* CONFIG_SPE */
1033 * extern void giveup_fpu(struct task_struct *prev)
1035 * Not all FSL Book-E cores have an FPU
1037 #ifndef CONFIG_PPC_FPU
1043 * extern void abort(void)
1045 * At present, this routine just applies a system reset.
1049 mtspr SPRN_DBCR0,r13 /* disable all debug events */
1052 ori r13,r13,MSR_DE@l /* Enable Debug Events */
1055 mfspr r13,SPRN_DBCR0
1056 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1057 mtspr SPRN_DBCR0,r13
1060 _GLOBAL(set_context)
1062 #ifdef CONFIG_BDI_SWITCH
1063 /* Context switch the PTE pointer for the Abatron BDI2000.
1064 * The PGDIR is the second parameter.
1066 lis r5, abatron_pteptrs@h
1067 ori r5, r5, abatron_pteptrs@l
1071 isync /* Force context change */
1075 * We put a few things here that have to be page-aligned. This stuff
1076 * goes at the beginning of the data segment, which is page-aligned.
1082 .globl empty_zero_page
1085 .globl swapper_pg_dir
1087 .space PGD_TABLE_SIZE
1090 * Room for two PTE pointers, usually the kernel and current user pointers
1091 * to their respective root page table.