3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/errno.h>
23 #include <linux/sys.h>
24 #include <linux/threads.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/unistd.h>
35 #undef SHOW_SYSCALLS_TASK
38 * MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE.
40 #if MSR_KERNEL >= 0x10000
41 #define LOAD_MSR_KERNEL(r, x) lis r,(x)@h; ori r,r,(x)@l
43 #define LOAD_MSR_KERNEL(r, x) li r,(x)
47 .globl mcheck_transfer_to_handler
48 mcheck_transfer_to_handler:
49 b transfer_to_handler_full
51 .globl debug_transfer_to_handler
52 debug_transfer_to_handler:
53 b transfer_to_handler_full
55 .globl crit_transfer_to_handler
56 crit_transfer_to_handler:
61 .globl crit_transfer_to_handler
62 crit_transfer_to_handler:
71 * This code finishes saving the registers to the exception frame
72 * and jumps to the appropriate handler for the exception, turning
73 * on address translation.
74 * Note that we rely on the caller having set cr0.eq iff the exception
75 * occurred in kernel mode (i.e. MSR:PR = 0).
77 .globl transfer_to_handler_full
78 transfer_to_handler_full:
82 .globl transfer_to_handler
94 tovirt(r2,r2) /* set r2 to current */
95 beq 2f /* if from user, fix up THREAD.regs */
96 addi r11,r1,STACK_FRAME_OVERHEAD
98 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
99 /* Check to see if the dbcr0 register is set up to debug. Use the
100 internal debug mode bit to do this. */
101 lwz r12,THREAD_DBCR0(r12)
102 andis. r12,r12,DBCR0_IDM@h
104 /* From user and task is ptraced - load up global dbcr0 */
105 li r12,-1 /* clear all pending debug events */
107 lis r11,global_dbcr0@ha
109 addi r11,r11,global_dbcr0@l
111 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
124 2: /* if from kernel, check interrupted DOZE/NAP mode and
125 * check for stack overflow
127 lwz r9,KSP_LIMIT(r12)
128 cmplw r1,r9 /* if r1 <= ksp_limit */
129 ble- stack_ovf /* then the kernel stack overflowed */
132 rlwinm r9,r1,0,0,31-THREAD_SHIFT
133 tophys(r9,r9) /* check local flags */
134 lwz r12,TI_LOCAL_FLAGS(r9)
136 bt- 31-TLF_NAPPING,4f
137 bt- 31-TLF_SLEEPING,7f
138 #endif /* CONFIG_6xx */
139 .globl transfer_to_handler_cont
140 transfer_to_handler_cont:
143 lwz r11,0(r9) /* virtual address of handler */
144 lwz r9,4(r9) /* where to go when done */
149 RFI /* jump to handler, enable MMU */
152 4: rlwinm r12,r12,0,~_TLF_NAPPING
153 stw r12,TI_LOCAL_FLAGS(r9)
154 b power_save_6xx_restore
156 7: rlwinm r12,r12,0,~_TLF_SLEEPING
157 stw r12,TI_LOCAL_FLAGS(r9)
158 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
159 rlwinm r9,r9,0,~MSR_EE
160 lwz r12,_LINK(r11) /* and return to address in LR */
161 b fast_exception_return
165 * On kernel stack overflow, load up an initial stack pointer
166 * and call StackOverflow(regs), which should not return.
169 /* sometimes we use a statically-allocated stack, which is OK. */
173 ble 5b /* r1 <= &_end is OK */
175 addi r3,r1,STACK_FRAME_OVERHEAD
176 lis r1,init_thread_union@ha
177 addi r1,r1,init_thread_union@l
178 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
179 lis r9,StackOverflow@ha
180 addi r9,r9,StackOverflow@l
181 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
189 * Handle a system call.
191 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
192 .stabs "entry_32.S",N_SO,0,0,0f
199 lwz r11,_CCR(r1) /* Clear SO bit in CR */
204 #endif /* SHOW_SYSCALLS */
205 rlwinm r10,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
206 lwz r11,TI_FLAGS(r10)
207 andi. r11,r11,_TIF_SYSCALL_T_OR_A
209 syscall_dotrace_cont:
210 cmplwi 0,r0,NR_syscalls
211 lis r10,sys_call_table@h
212 ori r10,r10,sys_call_table@l
215 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
217 addi r9,r1,STACK_FRAME_OVERHEAD
219 blrl /* Call handler */
220 .globl ret_from_syscall
223 bl do_show_syscall_exit
226 rlwinm r12,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
227 /* disable interrupts so current_thread_info()->flags can't change */
228 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
233 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
234 bne- syscall_exit_work
236 blt+ syscall_exit_cont
237 lwz r11,_CCR(r1) /* Load CR */
239 oris r11,r11,0x1000 /* Set SO bit in CR */
242 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
243 /* If the process has its own DBCR0 value, load it up. The internal
244 debug mode bit tells us that dbcr0 should be loaded. */
245 lwz r0,THREAD+THREAD_DBCR0(r2)
246 andis. r10,r0,DBCR0_IDM@h
250 lis r4,icache_44x_need_flush@ha
251 lwz r5,icache_44x_need_flush@l(r4)
255 #endif /* CONFIG_44x */
258 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
259 stwcx. r0,0,r1 /* to clear the reservation */
276 stw r7,icache_44x_need_flush@l(r4)
278 #endif /* CONFIG_44x */
290 /* Traced system call support */
295 addi r3,r1,STACK_FRAME_OVERHEAD
296 bl do_syscall_trace_enter
297 lwz r0,GPR0(r1) /* Restore original registers */
305 b syscall_dotrace_cont
308 andi. r0,r9,_TIF_RESTOREALL
314 andi. r0,r9,_TIF_NOERROR
316 lwz r11,_CCR(r1) /* Load CR */
318 oris r11,r11,0x1000 /* Set SO bit in CR */
321 1: stw r6,RESULT(r1) /* Save result */
322 stw r3,GPR3(r1) /* Update return value */
323 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
326 /* Clear per-syscall TIF flags if any are set. */
328 li r11,_TIF_PERSYSCALL_MASK
329 addi r12,r12,TI_FLAGS
332 #ifdef CONFIG_IBM405_ERR77
337 subi r12,r12,TI_FLAGS
339 4: /* Anything which requires enabling interrupts? */
340 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
343 /* Re-enable interrupts */
348 /* Save NVGPRS if they're not saved already */
356 addi r3,r1,STACK_FRAME_OVERHEAD
357 bl do_syscall_trace_leave
358 b ret_from_except_full
362 #ifdef SHOW_SYSCALLS_TASK
363 lis r11,show_syscalls_task@ha
364 lwz r11,show_syscalls_task@l(r11)
395 do_show_syscall_exit:
396 #ifdef SHOW_SYSCALLS_TASK
397 lis r11,show_syscalls_task@ha
398 lwz r11,show_syscalls_task@l(r11)
404 stw r3,RESULT(r1) /* Save result */
414 7: .string "syscall %d(%x, %x, %x, %x, %x, "
415 77: .string "%x), current=%p\n"
416 79: .string " -> %x\n"
419 #ifdef SHOW_SYSCALLS_TASK
421 .globl show_syscalls_task
426 #endif /* SHOW_SYSCALLS */
429 * The fork/clone functions need to copy the full register set into
430 * the child process. Therefore we need to save all the nonvolatile
431 * registers (r13 - r31) before calling the C code.
437 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
438 stw r0,_TRAP(r1) /* register set saved */
445 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
446 stw r0,_TRAP(r1) /* register set saved */
453 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
454 stw r0,_TRAP(r1) /* register set saved */
457 .globl ppc_swapcontext
461 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
462 stw r0,_TRAP(r1) /* register set saved */
466 * Top-level page fault handling.
467 * This is in assembler because if do_page_fault tells us that
468 * it is a bad kernel page fault, we want to save the non-volatile
469 * registers before calling bad_page_fault.
471 .globl handle_page_fault
474 addi r3,r1,STACK_FRAME_OVERHEAD
483 addi r3,r1,STACK_FRAME_OVERHEAD
486 b ret_from_except_full
489 * This routine switches between two different tasks. The process
490 * state of one is saved on its kernel stack. Then the state
491 * of the other is restored from its kernel stack. The memory
492 * management hardware is updated to the second process's state.
493 * Finally, we can return to the second process.
494 * On entry, r3 points to the THREAD for the current task, r4
495 * points to the THREAD for the new task.
497 * This routine is always called with interrupts disabled.
499 * Note: there are two ways to get to the "going out" portion
500 * of this code; either by coming in via the entry (_switch)
501 * or via "fork" which must set up an environment equivalent
502 * to the "_switch" path. If you change this , you'll have to
503 * change the fork code also.
505 * The code which creates the new task context is in 'copy_thread'
506 * in arch/ppc/kernel/process.c
509 stwu r1,-INT_FRAME_SIZE(r1)
511 stw r0,INT_FRAME_SIZE+4(r1)
512 /* r3-r12 are caller saved -- Cort */
514 stw r0,_NIP(r1) /* Return to switch caller */
516 li r0,MSR_FP /* Disable floating-point */
517 #ifdef CONFIG_ALTIVEC
519 oris r0,r0,MSR_VEC@h /* Disable altivec */
520 mfspr r12,SPRN_VRSAVE /* save vrsave register value */
521 stw r12,THREAD+THREAD_VRSAVE(r2)
522 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
523 #endif /* CONFIG_ALTIVEC */
526 oris r0,r0,MSR_SPE@h /* Disable SPE */
527 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
528 stw r12,THREAD+THREAD_SPEFSCR(r2)
529 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
530 #endif /* CONFIG_SPE */
531 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
539 stw r1,KSP(r3) /* Set old stack pointer */
542 /* We need a sync somewhere here to make sure that if the
543 * previous task gets rescheduled on another CPU, it sees all
544 * stores it has performed on this one.
547 #endif /* CONFIG_SMP */
551 mtspr SPRN_SPRG3,r0 /* Update current THREAD phys addr */
552 lwz r1,KSP(r4) /* Load new stack pointer */
554 /* save the old current 'last' for return value */
556 addi r2,r4,-THREAD /* Update current */
558 #ifdef CONFIG_ALTIVEC
560 lwz r0,THREAD+THREAD_VRSAVE(r2)
561 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
562 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
563 #endif /* CONFIG_ALTIVEC */
566 lwz r0,THREAD+THREAD_SPEFSCR(r2)
567 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
568 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
569 #endif /* CONFIG_SPE */
573 /* r3-r12 are destroyed -- Cort */
576 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
578 addi r1,r1,INT_FRAME_SIZE
581 .globl fast_exception_return
582 fast_exception_return:
583 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
584 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
585 beq 1f /* if not, we've got problems */
588 2: REST_4GPRS(3, r11)
603 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
604 /* check if the exception happened in a restartable section */
605 1: lis r3,exc_exit_restart_end@ha
606 addi r3,r3,exc_exit_restart_end@l
609 lis r4,exc_exit_restart@ha
610 addi r4,r4,exc_exit_restart@l
613 lis r3,fee_restarts@ha
615 lwz r5,fee_restarts@l(r3)
617 stw r5,fee_restarts@l(r3)
618 mr r12,r4 /* restart at exc_exit_restart */
627 /* aargh, a nonrecoverable interrupt, panic */
628 /* aargh, we don't know which trap this is */
629 /* but the 601 doesn't implement the RI bit, so assume it's OK */
633 END_FTR_SECTION_IFSET(CPU_FTR_601)
636 addi r3,r1,STACK_FRAME_OVERHEAD
638 ori r10,r10,MSR_KERNEL@l
639 bl transfer_to_handler_full
640 .long nonrecoverable_exception
641 .long ret_from_except
644 .globl ret_from_except_full
645 ret_from_except_full:
649 .globl ret_from_except
651 /* Hard-disable interrupts so that current_thread_info()->flags
652 * can't change between when we test it and when we return
653 * from the interrupt. */
654 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
655 SYNC /* Some chip revs have problems here... */
656 MTMSRD(r10) /* disable interrupts */
658 lwz r3,_MSR(r1) /* Returning to user mode? */
662 user_exc_return: /* r10 contains MSR_KERNEL here */
663 /* Check current_thread_info()->flags */
664 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
666 andi. r0,r9,_TIF_USER_WORK_MASK
670 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
671 /* Check whether this process has its own DBCR0 value. The internal
672 debug mode bit tells us that dbcr0 should be loaded. */
673 lwz r0,THREAD+THREAD_DBCR0(r2)
674 andis. r10,r0,DBCR0_IDM@h
678 #ifdef CONFIG_PREEMPT
681 /* N.B. the only way to get here is from the beq following ret_from_except. */
683 /* check current_thread_info->preempt_count */
684 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
685 lwz r0,TI_PREEMPT(r9)
686 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
689 andi. r0,r0,_TIF_NEED_RESCHED
691 andi. r0,r3,MSR_EE /* interrupts off? */
692 beq restore /* don't schedule if so */
693 1: bl preempt_schedule_irq
694 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
696 andi. r0,r3,_TIF_NEED_RESCHED
700 #endif /* CONFIG_PREEMPT */
702 /* interrupts are hard-disabled at this point */
705 lis r4,icache_44x_need_flush@ha
706 lwz r5,icache_44x_need_flush@l(r4)
711 stw r6,icache_44x_need_flush@l(r4)
713 #endif /* CONFIG_44x */
727 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
728 stwcx. r0,0,r1 /* to clear the reservation */
730 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
732 andi. r10,r9,MSR_RI /* check if this exception occurred */
733 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
741 * Once we put values in SRR0 and SRR1, we are in a state
742 * where exceptions are not recoverable, since taking an
743 * exception will trash SRR0 and SRR1. Therefore we clear the
744 * MSR:RI bit to indicate this. If we do take an exception,
745 * we can't return to the point of the exception but we
746 * can restart the exception exit path at the label
747 * exc_exit_restart below. -- paulus
749 LOAD_MSR_KERNEL(r10,MSR_KERNEL & ~MSR_RI)
751 MTMSRD(r10) /* clear the RI bit */
752 .globl exc_exit_restart
761 .globl exc_exit_restart_end
762 exc_exit_restart_end:
766 #else /* !(CONFIG_4xx || CONFIG_BOOKE) */
768 * This is a bit different on 4xx/Book-E because it doesn't have
769 * the RI bit in the MSR.
770 * The TLB miss handler checks if we have interrupted
771 * the exception exit path and restarts it if so
772 * (well maybe one day it will... :).
779 .globl exc_exit_restart
788 .globl exc_exit_restart_end
789 exc_exit_restart_end:
792 b . /* prevent prefetch past rfi */
795 * Returning from a critical interrupt in user mode doesn't need
796 * to be any different from a normal exception. For a critical
797 * interrupt in the kernel, we just return (without checking for
798 * preemption) since the interrupt may have happened at some crucial
799 * place (e.g. inside the TLB miss handler), and because we will be
800 * running with r1 pointing into critical_stack, not the current
801 * process's kernel stack (and therefore current_thread_info() will
802 * give the wrong answer).
803 * We have to restore various SPRs that may have been in use at the
804 * time of the critical interrupt.
808 #define PPC_40x_TURN_OFF_MSR_DR \
809 /* avoid any possible TLB misses here by turning off MSR.DR, we \
810 * assume the instructions here are mapped by a pinned TLB entry */ \
816 #define PPC_40x_TURN_OFF_MSR_DR
819 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
822 andi. r3,r3,MSR_PR; \
823 LOAD_MSR_KERNEL(r10,MSR_KERNEL); \
824 bne user_exc_return; \
831 mtspr SPRN_XER,r10; \
833 PPC405_ERR77(0,r1); \
834 stwcx. r0,0,r1; /* to clear the reservation */ \
839 PPC_40x_TURN_OFF_MSR_DR; \
842 mtspr SPRN_DEAR,r9; \
843 mtspr SPRN_ESR,r10; \
846 mtspr exc_lvl_srr0,r11; \
847 mtspr exc_lvl_srr1,r12; \
855 b .; /* prevent prefetch past exc_lvl_rfi */
857 .globl ret_from_crit_exc
859 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, RFCI)
862 .globl ret_from_debug_exc
864 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, RFDI)
866 .globl ret_from_mcheck_exc
868 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, RFMCI)
869 #endif /* CONFIG_BOOKE */
872 * Load the DBCR0 value for a task that is being ptraced,
873 * having first saved away the global DBCR0. Note that r0
874 * has the dbcr0 value to set upon entry to this.
877 mfmsr r10 /* first disable debug exceptions */
878 rlwinm r10,r10,0,~MSR_DE
882 lis r11,global_dbcr0@ha
883 addi r11,r11,global_dbcr0@l
885 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
896 mtspr SPRN_DBSR,r11 /* clear all pending debug events */
904 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
906 do_work: /* r10 contains MSR_KERNEL here */
907 andi. r0,r9,_TIF_NEED_RESCHED
910 do_resched: /* r10 contains MSR_KERNEL here */
913 MTMSRD(r10) /* hard-enable interrupts */
916 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
918 MTMSRD(r10) /* disable interrupts */
919 rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
921 andi. r0,r9,_TIF_NEED_RESCHED
923 andi. r0,r9,_TIF_USER_WORK_MASK
925 do_user_signal: /* r10 contains MSR_KERNEL here */
928 MTMSRD(r10) /* hard-enable interrupts */
929 /* save r13-r31 in the exception frame, if not already done */
937 addi r4,r1,STACK_FRAME_OVERHEAD
943 * We come here when we are at the end of handling an exception
944 * that occurred at a place where taking an exception will lose
945 * state information, such as the contents of SRR0 and SRR1.
948 lis r10,exc_exit_restart_end@ha
949 addi r10,r10,exc_exit_restart_end@l
952 lis r11,exc_exit_restart@ha
953 addi r11,r11,exc_exit_restart@l
956 lis r10,ee_restarts@ha
957 lwz r12,ee_restarts@l(r10)
959 stw r12,ee_restarts@l(r10)
960 mr r12,r11 /* restart at exc_exit_restart */
962 3: /* OK, we can't recover, kill this process */
963 /* but the 601 doesn't implement the RI bit, so assume it's OK */
966 END_FTR_SECTION_IFSET(CPU_FTR_601)
973 4: addi r3,r1,STACK_FRAME_OVERHEAD
974 bl nonrecoverable_exception
975 /* shouldn't return */
985 * PROM code for specific machines follows. Put it
986 * here so it's easy to add arch-specific sections later.
989 #ifdef CONFIG_PPC_RTAS
991 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
992 * called with the MMU off.
995 stwu r1,-INT_FRAME_SIZE(r1)
997 stw r0,INT_FRAME_SIZE+4(r1)
998 LOAD_REG_ADDR(r4, rtas)
999 lis r6,1f@ha /* physical return address for rtas */
1003 lwz r8,RTASENTRY(r4)
1007 LOAD_MSR_KERNEL(r0,MSR_KERNEL)
1008 SYNC /* disable interrupts so SRR0/1 */
1009 MTMSRD(r0) /* don't get trashed */
1010 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1017 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1018 lwz r9,8(r9) /* original msr value */
1020 addi r1,r1,INT_FRAME_SIZE
1025 RFI /* return to caller */
1027 .globl machine_check_in_rtas
1028 machine_check_in_rtas:
1030 /* XXX load up BATs and panic */
1032 #endif /* CONFIG_PPC_RTAS */