1 #ifndef _ASM_POWERPC_PGTABLE_PPC64_H_
2 #define _ASM_POWERPC_PGTABLE_PPC64_H_
4 * This file contains the functions and defines necessary to modify and use
5 * the ppc64 hashed page table.
9 #include <linux/stddef.h>
10 #include <asm/tlbflush.h>
11 #endif /* __ASSEMBLY__ */
13 #ifdef CONFIG_PPC_64K_PAGES
14 #include <asm/pgtable-ppc64-64k.h>
16 #include <asm/pgtable-ppc64-4k.h>
19 #define FIRST_USER_ADDRESS 0
22 * Size of EA range mapped by our pagetables.
24 #define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
25 PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
26 #define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
29 /* Some sanity checking */
30 #if TASK_SIZE_USER64 > PGTABLE_RANGE
31 #error TASK_SIZE_USER64 exceeds pagetable range
34 #if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
35 #error TASK_SIZE_USER64 exceeds user VSID range
39 * Define the address range of the vmalloc VM area.
41 #define VMALLOC_START ASM_CONST(0xD000000000000000)
42 #define VMALLOC_SIZE (PGTABLE_RANGE >> 1)
43 #define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE)
46 * Define the address ranges for MMIO and IO space :
48 * ISA_IO_BASE = VMALLOC_END, 64K reserved area
49 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
50 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
52 #define FULL_IO_SIZE 0x80000000ul
53 #define ISA_IO_BASE (VMALLOC_END)
54 #define ISA_IO_END (VMALLOC_END + 0x10000ul)
55 #define PHB_IO_BASE (ISA_IO_END)
56 #define PHB_IO_END (VMALLOC_END + FULL_IO_SIZE)
57 #define IOREMAP_BASE (PHB_IO_END)
58 #define IOREMAP_END (VMALLOC_START + PGTABLE_RANGE)
63 #define REGION_SHIFT 60UL
64 #define REGION_MASK (0xfUL << REGION_SHIFT)
65 #define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT)
67 #define VMALLOC_REGION_ID (REGION_ID(VMALLOC_START))
68 #define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET))
69 #define VMEMMAP_REGION_ID (0xfUL)
70 #define USER_REGION_ID (0UL)
73 * Defines the address of the vmemap area, in its own region
75 #define VMEMMAP_BASE (VMEMMAP_REGION_ID << REGION_SHIFT)
76 #define vmemmap ((struct page *)VMEMMAP_BASE)
80 * Include the PTE bits definitions
82 #include <asm/pte-hash64.h>
84 /* Some other useful definitions */
85 #define PTE_RPN_MAX (1UL << (64 - PTE_RPN_SHIFT))
86 #define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))
88 /* _PAGE_CHG_MASK masks of bits that are to be preserved accross
91 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
92 _PAGE_ACCESSED | _PAGE_SPECIAL)
94 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
95 #define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT)
98 /* Permission masks used to generate the __P and __S table,
100 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
102 #define PAGE_NONE __pgprot(_PAGE_BASE)
103 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
104 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
105 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
106 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
107 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
108 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
110 /* Permission masks used for kernel mappings */
111 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
112 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
114 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
115 _PAGE_NO_CACHE | _PAGE_GUARDED)
116 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW | _PAGE_EXEC)
117 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
118 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO | _PAGE_EXEC)
120 /* Protection bits for use by pte_pgprot() */
121 #define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | \
122 _PAGE_NO_CACHE | _PAGE_WRITETHRU | \
123 _PAGE_4K_PFN | _PAGE_USER | _PAGE_RW | \
124 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_EXEC)
127 /* We always have _PAGE_SPECIAL on 64 bit */
128 #define __HAVE_ARCH_PTE_SPECIAL
130 /* Make modules code happy. We don't set RO yet */
131 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X
134 * POWER4 and newer have per page execute protection, older chips can only
135 * do this on a segment (256MB) basis.
137 * Also, write permissions imply read permissions.
138 * This is the closest we can get..
140 * Note due to the way vm flags are laid out, the bits are XWR
142 #define __P000 PAGE_NONE
143 #define __P001 PAGE_READONLY
144 #define __P010 PAGE_COPY
145 #define __P011 PAGE_COPY
146 #define __P100 PAGE_READONLY_X
147 #define __P101 PAGE_READONLY_X
148 #define __P110 PAGE_COPY_X
149 #define __P111 PAGE_COPY_X
151 #define __S000 PAGE_NONE
152 #define __S001 PAGE_READONLY
153 #define __S010 PAGE_SHARED
154 #define __S011 PAGE_SHARED
155 #define __S100 PAGE_READONLY_X
156 #define __S101 PAGE_READONLY_X
157 #define __S110 PAGE_SHARED_X
158 #define __S111 PAGE_SHARED_X
160 #ifdef CONFIG_PPC_MM_SLICES
161 #define HAVE_ARCH_UNMAPPED_AREA
162 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
163 #endif /* CONFIG_PPC_MM_SLICES */
168 * This is the default implementation of various PTE accessors, it's
169 * used in all cases except Book3S with 64K pages where we have a
170 * concept of sub-pages
174 #ifdef STRICT_MM_TYPECHECKS
175 #define __real_pte(e,p) ((real_pte_t){(e)})
176 #define __rpte_to_pte(r) ((r).pte)
178 #define __real_pte(e,p) (e)
179 #define __rpte_to_pte(r) (__pte(r))
181 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> 12)
183 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
186 shift = mmu_psize_defs[psize].shift; \
188 #define pte_iterate_hashed_end() } while(0)
190 #ifdef CONFIG_PPC_HAS_HASH_64K
191 #define pte_pagesize_index(mm, addr, pte) get_slice_psize(mm, addr)
193 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
196 #endif /* __real_pte */
200 * Conversion functions: convert a page and protection to a page entry,
201 * and a page entry and page directory to the page they refer to.
203 * mk_pte takes a (struct page *) as input
205 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
207 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
212 pte_val(pte) = (pfn << PTE_RPN_SHIFT) | pgprot_val(pgprot);
216 #define pte_modify(_pte, newprot) \
217 (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)))
219 #define pte_none(pte) ((pte_val(pte) & ~_PAGE_HPTEFLAGS) == 0)
220 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
222 /* pte_clear moved to later in this file */
224 #define pte_pfn(x) ((unsigned long)((pte_val(x)>>PTE_RPN_SHIFT)))
225 #define pte_page(x) pfn_to_page(pte_pfn(x))
227 #define PMD_BAD_BITS (PTE_TABLE_SIZE-1)
228 #define PUD_BAD_BITS (PMD_TABLE_SIZE-1)
230 #define pmd_set(pmdp, pmdval) (pmd_val(*(pmdp)) = (pmdval))
231 #define pmd_none(pmd) (!pmd_val(pmd))
232 #define pmd_bad(pmd) (!is_kernel_addr(pmd_val(pmd)) \
233 || (pmd_val(pmd) & PMD_BAD_BITS))
234 #define pmd_present(pmd) (pmd_val(pmd) != 0)
235 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0)
236 #define pmd_page_vaddr(pmd) (pmd_val(pmd) & ~PMD_MASKED_BITS)
237 #define pmd_page(pmd) virt_to_page(pmd_page_vaddr(pmd))
239 #define pud_set(pudp, pudval) (pud_val(*(pudp)) = (pudval))
240 #define pud_none(pud) (!pud_val(pud))
241 #define pud_bad(pud) (!is_kernel_addr(pud_val(pud)) \
242 || (pud_val(pud) & PUD_BAD_BITS))
243 #define pud_present(pud) (pud_val(pud) != 0)
244 #define pud_clear(pudp) (pud_val(*(pudp)) = 0)
245 #define pud_page_vaddr(pud) (pud_val(pud) & ~PUD_MASKED_BITS)
246 #define pud_page(pud) virt_to_page(pud_page_vaddr(pud))
248 #define pgd_set(pgdp, pudp) ({pgd_val(*(pgdp)) = (unsigned long)(pudp);})
251 * Find an entry in a page-table-directory. We combine the address region
252 * (the high order N bits) and the pgd portion of the address.
254 /* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
255 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)
257 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
259 #define pmd_offset(pudp,addr) \
260 (((pmd_t *) pud_page_vaddr(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
262 #define pte_offset_kernel(dir,addr) \
263 (((pte_t *) pmd_page_vaddr(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
265 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
266 #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
267 #define pte_unmap(pte) do { } while(0)
268 #define pte_unmap_nested(pte) do { } while(0)
270 /* to find an entry in a kernel page-table-directory */
271 /* This now only contains the vmalloc pages */
272 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
275 * The following only work if pte_present() is true.
276 * Undefined behaviour if not..
278 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW;}
279 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY;}
280 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED;}
281 static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE;}
282 static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }
284 static inline pte_t pte_wrprotect(pte_t pte) {
285 pte_val(pte) &= ~(_PAGE_RW); return pte; }
286 static inline pte_t pte_mkclean(pte_t pte) {
287 pte_val(pte) &= ~(_PAGE_DIRTY); return pte; }
288 static inline pte_t pte_mkold(pte_t pte) {
289 pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
290 static inline pte_t pte_mkwrite(pte_t pte) {
291 pte_val(pte) |= _PAGE_RW; return pte; }
292 static inline pte_t pte_mkdirty(pte_t pte) {
293 pte_val(pte) |= _PAGE_DIRTY; return pte; }
294 static inline pte_t pte_mkyoung(pte_t pte) {
295 pte_val(pte) |= _PAGE_ACCESSED; return pte; }
296 static inline pte_t pte_mkhuge(pte_t pte) {
298 static inline pte_t pte_mkspecial(pte_t pte) {
299 pte_val(pte) |= _PAGE_SPECIAL; return pte; }
300 static inline pgprot_t pte_pgprot(pte_t pte)
302 return __pgprot(pte_val(pte) & PAGE_PROT_BITS);
305 /* Atomic PTE updates */
306 static inline unsigned long pte_update(struct mm_struct *mm,
308 pte_t *ptep, unsigned long clr,
311 unsigned long old, tmp;
313 __asm__ __volatile__(
314 "1: ldarx %0,0,%3 # pte_update\n\
320 : "=&r" (old), "=&r" (tmp), "=m" (*ptep)
321 : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY)
324 /* huge pages use the old page table lock */
326 assert_pte_locked(mm, addr);
328 if (old & _PAGE_HASHPTE)
329 hpte_need_flush(mm, addr, ptep, old, huge);
333 static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
334 unsigned long addr, pte_t *ptep)
338 if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
340 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0);
341 return (old & _PAGE_ACCESSED) != 0;
343 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
344 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
347 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
351 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
352 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
357 if ((pte_val(*ptep) & _PAGE_RW) == 0)
359 old = pte_update(mm, addr, ptep, _PAGE_RW, 0);
362 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
363 unsigned long addr, pte_t *ptep)
367 if ((pte_val(*ptep) & _PAGE_RW) == 0)
369 old = pte_update(mm, addr, ptep, _PAGE_RW, 1);
373 * We currently remove entries from the hashtable regardless of whether
374 * the entry was young or dirty. The generic routines only flush if the
375 * entry was young or dirty which is not good enough.
377 * We should be more intelligent about this but for the moment we override
378 * these functions and force a tlb flush unconditionally
380 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
381 #define ptep_clear_flush_young(__vma, __address, __ptep) \
383 int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
388 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
389 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
390 unsigned long addr, pte_t *ptep)
392 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0);
396 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
399 pte_update(mm, addr, ptep, ~0UL, 0);
403 /* Set the dirty and/or accessed bits atomically in a linux PTE, this
404 * function doesn't need to flush the hash entry
406 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
408 unsigned long bits = pte_val(entry) &
409 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW |
410 _PAGE_EXEC | _PAGE_HWEXEC);
411 unsigned long old, tmp;
413 __asm__ __volatile__(
420 :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
421 :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
425 #define __HAVE_ARCH_PTE_SAME
426 #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
428 #define pte_ERROR(e) \
429 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
430 #define pmd_ERROR(e) \
431 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
432 #define pgd_ERROR(e) \
433 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
435 /* Encode and de-code a swap entry */
436 #define __swp_type(entry) (((entry).val >> 1) & 0x3f)
437 #define __swp_offset(entry) ((entry).val >> 8)
438 #define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})
439 #define __pte_to_swp_entry(pte) ((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
440 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << PTE_RPN_SHIFT })
441 #define pte_to_pgoff(pte) (pte_val(pte) >> PTE_RPN_SHIFT)
442 #define pgoff_to_pte(off) ((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE})
443 #define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_RPN_SHIFT)
445 void pgtable_cache_init(void);
448 * find_linux_pte returns the address of a linux pte for a given
449 * effective address and directory. If not found, it returns zero.
450 */static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
457 pg = pgdir + pgd_index(ea);
458 if (!pgd_none(*pg)) {
459 pu = pud_offset(pg, ea);
460 if (!pud_none(*pu)) {
461 pm = pmd_offset(pu, ea);
462 if (pmd_present(*pm))
463 pt = pte_offset_kernel(pm, ea);
469 pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long address);
471 #endif /* __ASSEMBLY__ */
473 #endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */