2 * TQM 8560 Device Tree Source
4 * Copyright 2008 Freescale Semiconductor Inc.
5 * Copyright 2008 Wolfgang Grandegger <wg@grandegger.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
16 model = "tqc,tqm8560";
17 compatible = "tqc,tqm8560";
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
40 i-cache-size = <32768>;
41 timebase-frequency = <0>;
43 clock-frequency = <0>;
44 next-level-cache = <&L2>;
49 device_type = "memory";
50 reg = <0x00000000 0x10000000>;
57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x200>;
60 compatible = "fsl,mpc8560-immr", "simple-bus";
62 memory-controller@2000 {
63 compatible = "fsl,8540-memory-controller";
64 reg = <0x2000 0x1000>;
65 interrupt-parent = <&mpic>;
69 L2: l2-cache-controller@20000 {
70 compatible = "fsl,8540-l2-cache-controller";
71 reg = <0x20000 0x1000>;
72 cache-line-size = <32>;
73 cache-size = <0x40000>; // L2, 256K
74 interrupt-parent = <&mpic>;
82 compatible = "fsl-i2c";
85 interrupt-parent = <&mpic>;
89 compatible = "dallas,ds1337";
97 compatible = "fsl,gianfar-mdio";
100 phy1: ethernet-phy@1 {
101 interrupt-parent = <&mpic>;
104 device_type = "ethernet-phy";
106 phy2: ethernet-phy@2 {
107 interrupt-parent = <&mpic>;
110 device_type = "ethernet-phy";
112 phy3: ethernet-phy@3 {
113 interrupt-parent = <&mpic>;
116 device_type = "ethernet-phy";
120 enet0: ethernet@24000 {
122 device_type = "network";
124 compatible = "gianfar";
125 reg = <0x24000 0x1000>;
126 local-mac-address = [ 00 00 00 00 00 00 ];
127 interrupts = <29 2 30 2 34 2>;
128 interrupt-parent = <&mpic>;
129 phy-handle = <&phy2>;
132 enet1: ethernet@25000 {
134 device_type = "network";
136 compatible = "gianfar";
137 reg = <0x25000 0x1000>;
138 local-mac-address = [ 00 00 00 00 00 00 ];
139 interrupts = <35 2 36 2 40 2>;
140 interrupt-parent = <&mpic>;
141 phy-handle = <&phy1>;
145 interrupt-controller;
146 #address-cells = <0>;
147 #interrupt-cells = <2>;
148 reg = <0x40000 0x40000>;
149 device_type = "open-pic";
150 compatible = "chrp,open-pic";
154 #address-cells = <1>;
156 compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
157 reg = <0x919c0 0x30>;
161 #address-cells = <1>;
163 ranges = <0 0x80000 0x10000>;
166 compatible = "fsl,cpm-muram-data";
167 reg = <0 0x4000 0x9000 0x2000>;
172 compatible = "fsl,mpc8560-brg",
175 reg = <0x919f0 0x10 0x915f0 0x10>;
176 clock-frequency = <0>;
180 interrupt-controller;
181 #address-cells = <0>;
182 #interrupt-cells = <2>;
184 interrupt-parent = <&mpic>;
185 reg = <0x90c00 0x80>;
186 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
189 serial0: serial@91a00 {
190 device_type = "serial";
191 compatible = "fsl,mpc8560-scc-uart",
193 reg = <0x91a00 0x20 0x88000 0x100>;
195 fsl,cpm-command = <0x800000>;
196 current-speed = <115200>;
198 interrupt-parent = <&cpmpic>;
201 serial1: serial@91a20 {
202 device_type = "serial";
203 compatible = "fsl,mpc8560-scc-uart",
205 reg = <0x91a20 0x20 0x88100 0x100>;
207 fsl,cpm-command = <0x4a00000>;
208 current-speed = <115200>;
210 interrupt-parent = <&cpmpic>;
213 enet2: ethernet@91340 {
214 device_type = "network";
215 compatible = "fsl,mpc8560-fcc-enet",
217 reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
218 local-mac-address = [ 00 00 00 00 00 00 ];
219 fsl,cpm-command = <0x1a400300>;
221 interrupt-parent = <&cpmpic>;
222 phy-handle = <&phy3>;
228 compatible = "fsl,mpc8560-localbus", "fsl,pq3-localbus",
230 #address-cells = <2>;
232 reg = <0xe0005000 0x100>; // BRx, ORx, etc.
235 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
236 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
237 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527)
241 #address-cells = <1>;
243 compatible = "cfi-flash";
244 reg = <1 0x0 0x8000000>;
250 reg = <0x00000000 0x00200000>;
254 reg = <0x00200000 0x00300000>;
258 reg = <0x00500000 0x07a00000>;
262 reg = <0x07f00000 0x00040000>;
266 reg = <0x07f40000 0x00040000>;
270 reg = <0x07f80000 0x00080000>;
275 /* Note: CAN support needs be enabled in U-Boot */
277 compatible = "intel,82527"; // Bosch CC770
280 interrupt-parent = <&mpic>;
284 compatible = "intel,82527"; // Bosch CC770
285 reg = <2 0x100 0x100>;
287 interrupt-parent = <&mpic>;
293 #interrupt-cells = <1>;
295 #address-cells = <3>;
296 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
298 reg = <0xe0008000 0x1000>;
299 clock-frequency = <66666666>;
300 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
303 0xe000 0 0 1 &mpic 2 1
304 0xe000 0 0 2 &mpic 3 1>;
306 interrupt-parent = <&mpic>;
309 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
310 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;