arch/powerpc/boot/dts/mpc8572ds.dts

   1 /*
   2  * MPC8572 DS Device Tree Source
   3  *
   4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13 / {
  14         model = "fsl,MPC8572DS";
  15         compatible = "fsl,MPC8572DS";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 ethernet0 = &enet0;
  21                 ethernet1 = &enet1;
  22                 ethernet2 = &enet2;
  23                 ethernet3 = &enet3;
  24                 serial0 = &serial0;
  25                 serial1 = &serial1;
  26                 pci0 = &pci0;
  27                 pci1 = &pci1;
  28                 pci2 = &pci2;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 PowerPC,8572@0 {
  36                         device_type = "cpu";
  37                         reg = <0x0>;
  38                         d-cache-line-size = <32>;       // 32 bytes
  39                         i-cache-line-size = <32>;       // 32 bytes
  40                         d-cache-size = <0x8000>;                // L1, 32K
  41                         i-cache-size = <0x8000>;                // L1, 32K
  42                         timebase-frequency = <0>;
  43                         bus-frequency = <0>;
  44                         clock-frequency = <0>;
  45                         next-level-cache = <&L2>;
  46                 };
  47
  48                 PowerPC,8572@1 {
  49                         device_type = "cpu";
  50                         reg = <0x1>;
  51                         d-cache-line-size = <32>;       // 32 bytes
  52                         i-cache-line-size = <32>;       // 32 bytes
  53                         d-cache-size = <0x8000>;                // L1, 32K
  54                         i-cache-size = <0x8000>;                // L1, 32K
  55                         timebase-frequency = <0>;
  56                         bus-frequency = <0>;
  57                         clock-frequency = <0>;
  58                         next-level-cache = <&L2>;
  59                 };
  60         };
  61
  62         memory {
  63                 device_type = "memory";
  64         };
  65
  66         localbus@ffe05000 {
  67                 #address-cells = <2>;
  68                 #size-cells = <1>;
  69                 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
  70                 reg = <0 0xffe05000 0 0x1000>;
  71                 interrupts = <19 2>;
  72                 interrupt-parent = <&mpic>;
  73
  74                 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
  75                           0x1 0x0 0x0 0xe0000000 0x08000000
  76                           0x2 0x0 0x0 0xffa00000 0x00040000
  77                           0x3 0x0 0x0 0xffdf0000 0x00008000
  78                           0x4 0x0 0x0 0xffa40000 0x00040000
  79                           0x5 0x0 0x0 0xffa80000 0x00040000
  80                           0x6 0x0 0x0 0xffac0000 0x00040000>;
  81
  82                 nor@0,0 {
  83                         #address-cells = <1>;
  84                         #size-cells = <1>;
  85                         compatible = "cfi-flash";
  86                         reg = <0x0 0x0 0x8000000>;
  87                         bank-width = <2>;
  88                         device-width = <1>;
  89
  90                         ramdisk@0 {
  91                                 reg = <0x0 0x03000000>;
  92                                 readl-only;
  93                         };
  94
  95                         diagnostic@3000000 {
  96                                 reg = <0x03000000 0x00e00000>;
  97                                 read-only;
  98                         };
  99
 100                         dink@3e00000 {
 101                                 reg = <0x03e00000 0x00200000>;
 102                                 read-only;
 103                         };
 104
 105                         kernel@4000000 {
 106                                 reg = <0x04000000 0x00400000>;
 107                                 read-only;
 108                         };
 109
 110                         jffs2@4400000 {
 111                                 reg = <0x04400000 0x03b00000>;
 112                         };
 113
 114                         dtb@7f00000 {
 115                                 reg = <0x07f00000 0x00080000>;
 116                                 read-only;
 117                         };
 118
 119                         u-boot@7f80000 {
 120                                 reg = <0x07f80000 0x00080000>;
 121                                 read-only;
 122                         };
 123                 };
 124
 125                 nand@2,0 {
 126                         #address-cells = <1>;
 127                         #size-cells = <1>;
 128                         compatible = "fsl,mpc8572-fcm-nand",
 129                                      "fsl,elbc-fcm-nand";
 130                         reg = <0x2 0x0 0x40000>;
 131
 132                         u-boot@0 {
 133                                 reg = <0x0 0x02000000>;
 134                                 read-only;
 135                         };
 136
 137                         jffs2@2000000 {
 138                                 reg = <0x02000000 0x10000000>;
 139                         };
 140
 141                         ramdisk@12000000 {
 142                                 reg = <0x12000000 0x08000000>;
 143                                 read-only;
 144                         };
 145
 146                         kernel@1a000000 {
 147                                 reg = <0x1a000000 0x04000000>;
 148                         };
 149
 150                         dtb@1e000000 {
 151                                 reg = <0x1e000000 0x01000000>;
 152                                 read-only;
 153                         };
 154
 155                         empty@1f000000 {
 156                                 reg = <0x1f000000 0x21000000>;
 157                         };
 158                 };
 159
 160                 nand@4,0 {
 161                         compatible = "fsl,mpc8572-fcm-nand",
 162                                      "fsl,elbc-fcm-nand";
 163                         reg = <0x4 0x0 0x40000>;
 164                 };
 165
 166                 nand@5,0 {
 167                         compatible = "fsl,mpc8572-fcm-nand",
 168                                      "fsl,elbc-fcm-nand";
 169                         reg = <0x5 0x0 0x40000>;
 170                 };
 171
 172                 nand@6,0 {
 173                         compatible = "fsl,mpc8572-fcm-nand",
 174                                      "fsl,elbc-fcm-nand";
 175                         reg = <0x6 0x0 0x40000>;
 176                 };
 177         };
 178
 179         soc8572@ffe00000 {
 180                 #address-cells = <1>;
 181                 #size-cells = <1>;
 182                 device_type = "soc";
 183                 compatible = "simple-bus";
 184                 ranges = <0x0 0 0xffe00000 0x100000>;
 185                 reg = <0 0xffe00000 0 0x1000>;  // CCSRBAR & soc regs, remove once parse code for immrbase fixed
 186                 bus-frequency = <0>;            // Filled out by uboot.
 187
 188                 memory-controller@2000 {
 189                         compatible = "fsl,mpc8572-memory-controller";
 190                         reg = <0x2000 0x1000>;
 191                         interrupt-parent = <&mpic>;
 192                         interrupts = <18 2>;
 193                 };
 194
 195                 memory-controller@6000 {
 196                         compatible = "fsl,mpc8572-memory-controller";
 197                         reg = <0x6000 0x1000>;
 198                         interrupt-parent = <&mpic>;
 199                         interrupts = <18 2>;
 200                 };
 201
 202                 L2: l2-cache-controller@20000 {
 203                         compatible = "fsl,mpc8572-l2-cache-controller";
 204                         reg = <0x20000 0x1000>;
 205                         cache-line-size = <32>; // 32 bytes
 206                         cache-size = <0x100000>; // L2, 1M
 207                         interrupt-parent = <&mpic>;
 208                         interrupts = <16 2>;
 209                 };
 210
 211                 i2c@3000 {
 212                         #address-cells = <1>;
 213                         #size-cells = <0>;
 214                         cell-index = <0>;
 215                         compatible = "fsl-i2c";
 216                         reg = <0x3000 0x100>;
 217                         interrupts = <43 2>;
 218                         interrupt-parent = <&mpic>;
 219                         dfsrr;
 220                 };
 221
 222                 i2c@3100 {
 223                         #address-cells = <1>;
 224                         #size-cells = <0>;
 225                         cell-index = <1>;
 226                         compatible = "fsl-i2c";
 227                         reg = <0x3100 0x100>;
 228                         interrupts = <43 2>;
 229                         interrupt-parent = <&mpic>;
 230                         dfsrr;
 231                 };
 232
 233                 dma@c300 {
 234                         #address-cells = <1>;
 235                         #size-cells = <1>;
 236                         compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
 237                         reg = <0xc300 0x4>;
 238                         ranges = <0x0 0xc100 0x200>;
 239                         cell-index = <1>;
 240                         dma-channel@0 {
 241                                 compatible = "fsl,mpc8572-dma-channel",
 242                                                 "fsl,eloplus-dma-channel";
 243                                 reg = <0x0 0x80>;
 244                                 cell-index = <0>;
 245                                 interrupt-parent = <&mpic>;
 246                                 interrupts = <76 2>;
 247                         };
 248                         dma-channel@80 {
 249                                 compatible = "fsl,mpc8572-dma-channel",
 250                                                 "fsl,eloplus-dma-channel";
 251                                 reg = <0x80 0x80>;
 252                                 cell-index = <1>;
 253                                 interrupt-parent = <&mpic>;
 254                                 interrupts = <77 2>;
 255                         };
 256                         dma-channel@100 {
 257                                 compatible = "fsl,mpc8572-dma-channel",
 258                                                 "fsl,eloplus-dma-channel";
 259                                 reg = <0x100 0x80>;
 260                                 cell-index = <2>;
 261                                 interrupt-parent = <&mpic>;
 262                                 interrupts = <78 2>;
 263                         };
 264                         dma-channel@180 {
 265                                 compatible = "fsl,mpc8572-dma-channel",
 266                                                 "fsl,eloplus-dma-channel";
 267                                 reg = <0x180 0x80>;
 268                                 cell-index = <3>;
 269                                 interrupt-parent = <&mpic>;
 270                                 interrupts = <79 2>;
 271                         };
 272                 };
 273
 274                 dma@21300 {
 275                         #address-cells = <1>;
 276                         #size-cells = <1>;
 277                         compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
 278                         reg = <0x21300 0x4>;
 279                         ranges = <0x0 0x21100 0x200>;
 280                         cell-index = <0>;
 281                         dma-channel@0 {
 282                                 compatible = "fsl,mpc8572-dma-channel",
 283                                                 "fsl,eloplus-dma-channel";
 284                                 reg = <0x0 0x80>;
 285                                 cell-index = <0>;
 286                                 interrupt-parent = <&mpic>;
 287                                 interrupts = <20 2>;
 288                         };
 289                         dma-channel@80 {
 290                                 compatible = "fsl,mpc8572-dma-channel",
 291                                                 "fsl,eloplus-dma-channel";
 292                                 reg = <0x80 0x80>;
 293                                 cell-index = <1>;
 294                                 interrupt-parent = <&mpic>;
 295                                 interrupts = <21 2>;
 296                         };
 297                         dma-channel@100 {
 298                                 compatible = "fsl,mpc8572-dma-channel",
 299                                                 "fsl,eloplus-dma-channel";
 300                                 reg = <0x100 0x80>;
 301                                 cell-index = <2>;
 302                                 interrupt-parent = <&mpic>;
 303                                 interrupts = <22 2>;
 304                         };
 305                         dma-channel@180 {
 306                                 compatible = "fsl,mpc8572-dma-channel",
 307                                                 "fsl,eloplus-dma-channel";
 308                                 reg = <0x180 0x80>;
 309                                 cell-index = <3>;
 310                                 interrupt-parent = <&mpic>;
 311                                 interrupts = <23 2>;
 312                         };
 313                 };
 314
 315                 mdio@24520 {
 316                         #address-cells = <1>;
 317                         #size-cells = <0>;
 318                         compatible = "fsl,gianfar-mdio";
 319                         reg = <0x24520 0x20>;
 320
 321                         phy0: ethernet-phy@0 {
 322                                 interrupt-parent = <&mpic>;
 323                                 interrupts = <10 1>;
 324                                 reg = <0x0>;
 325                         };
 326                         phy1: ethernet-phy@1 {
 327                                 interrupt-parent = <&mpic>;
 328                                 interrupts = <10 1>;
 329                                 reg = <0x1>;
 330                         };
 331                         phy2: ethernet-phy@2 {
 332                                 interrupt-parent = <&mpic>;
 333                                 interrupts = <10 1>;
 334                                 reg = <0x2>;
 335                         };
 336                         phy3: ethernet-phy@3 {
 337                                 interrupt-parent = <&mpic>;
 338                                 interrupts = <10 1>;
 339                                 reg = <0x3>;
 340                         };
 341                 };
 342
 343                 enet0: ethernet@24000 {
 344                         cell-index = <0>;
 345                         device_type = "network";
 346                         model = "eTSEC";
 347                         compatible = "gianfar";
 348                         reg = <0x24000 0x1000>;
 349                         local-mac-address = [ 00 00 00 00 00 00 ];
 350                         interrupts = <29 2 30 2 34 2>;
 351                         interrupt-parent = <&mpic>;
 352                         phy-handle = <&phy0>;
 353                         phy-connection-type = "rgmii-id";
 354                 };
 355
 356                 enet1: ethernet@25000 {
 357                         cell-index = <1>;
 358                         device_type = "network";
 359                         model = "eTSEC";
 360                         compatible = "gianfar";
 361                         reg = <0x25000 0x1000>;
 362                         local-mac-address = [ 00 00 00 00 00 00 ];
 363                         interrupts = <35 2 36 2 40 2>;
 364                         interrupt-parent = <&mpic>;
 365                         phy-handle = <&phy1>;
 366                         phy-connection-type = "rgmii-id";
 367                 };
 368
 369                 enet2: ethernet@26000 {
 370                         cell-index = <2>;
 371                         device_type = "network";
 372                         model = "eTSEC";
 373                         compatible = "gianfar";
 374                         reg = <0x26000 0x1000>;
 375                         local-mac-address = [ 00 00 00 00 00 00 ];
 376                         interrupts = <31 2 32 2 33 2>;
 377                         interrupt-parent = <&mpic>;
 378                         phy-handle = <&phy2>;
 379                         phy-connection-type = "rgmii-id";
 380                 };
 381
 382                 enet3: ethernet@27000 {
 383                         cell-index = <3>;
 384                         device_type = "network";
 385                         model = "eTSEC";
 386                         compatible = "gianfar";
 387                         reg = <0x27000 0x1000>;
 388                         local-mac-address = [ 00 00 00 00 00 00 ];
 389                         interrupts = <37 2 38 2 39 2>;
 390                         interrupt-parent = <&mpic>;
 391                         phy-handle = <&phy3>;
 392                         phy-connection-type = "rgmii-id";
 393                 };
 394
 395                 serial0: serial@4500 {
 396                         cell-index = <0>;
 397                         device_type = "serial";
 398                         compatible = "ns16550";
 399                         reg = <0x4500 0x100>;
 400                         clock-frequency = <0>;
 401                         interrupts = <42 2>;
 402                         interrupt-parent = <&mpic>;
 403                 };
 404
 405                 serial1: serial@4600 {
 406                         cell-index = <1>;
 407                         device_type = "serial";
 408                         compatible = "ns16550";
 409                         reg = <0x4600 0x100>;
 410                         clock-frequency = <0>;
 411                         interrupts = <42 2>;
 412                         interrupt-parent = <&mpic>;
 413                 };
 414
 415                 global-utilities@e0000 {        //global utilities block
 416                         compatible = "fsl,mpc8572-guts";
 417                         reg = <0xe0000 0x1000>;
 418                         fsl,has-rstcr;
 419                 };
 420
 421                 msi@41600 {
 422                         compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
 423                         reg = <0x41600 0x80>;
 424                         msi-available-ranges = <0 0x100>;
 425                         interrupts = <
 426                                 0xe0 0
 427                                 0xe1 0
 428                                 0xe2 0
 429                                 0xe3 0
 430                                 0xe4 0
 431                                 0xe5 0
 432                                 0xe6 0
 433                                 0xe7 0>;
 434                         interrupt-parent = <&mpic>;
 435                 };
 436
 437                 crypto@30000 {
 438                         compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
 439                                      "fsl,sec2.1", "fsl,sec2.0";
 440                         reg = <0x30000 0x10000>;
 441                         interrupts = <45 2 58 2>;
 442                         interrupt-parent = <&mpic>;
 443                         fsl,num-channels = <4>;
 444                         fsl,channel-fifo-len = <24>;
 445                         fsl,exec-units-mask = <0x9fe>;
 446                         fsl,descriptor-types-mask = <0x3ab0ebf>;
 447                 };
 448
 449                 mpic: pic@40000 {
 450                         interrupt-controller;
 451                         #address-cells = <0>;
 452                         #interrupt-cells = <2>;
 453                         reg = <0x40000 0x40000>;
 454                         compatible = "chrp,open-pic";
 455                         device_type = "open-pic";
 456                 };
 457         };
 458
 459         pci0: pcie@ffe08000 {
 460                 cell-index = <0>;
 461                 compatible = "fsl,mpc8548-pcie";
 462                 device_type = "pci";
 463                 #interrupt-cells = <1>;
 464                 #size-cells = <2>;
 465                 #address-cells = <3>;
 466                 reg = <0 0xffe08000 0 0x1000>;
 467                 bus-range = <0 255>;
 468                 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
 469                           0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>;
 470                 clock-frequency = <33333333>;
 471                 interrupt-parent = <&mpic>;
 472                 interrupts = <24 2>;
 473                 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
 474                 interrupt-map = <
 475                         /* IDSEL 0x11 func 0 - PCI slot 1 */
 476                         0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
 477                         0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
 478                         0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
 479                         0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
 480
 481                         /* IDSEL 0x11 func 1 - PCI slot 1 */
 482                         0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
 483                         0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
 484                         0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
 485                         0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
 486
 487                         /* IDSEL 0x11 func 2 - PCI slot 1 */
 488                         0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
 489                         0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
 490                         0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
 491                         0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
 492
 493                         /* IDSEL 0x11 func 3 - PCI slot 1 */
 494                         0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
 495                         0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
 496                         0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
 497                         0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
 498
 499                         /* IDSEL 0x11 func 4 - PCI slot 1 */
 500                         0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
 501                         0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
 502                         0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
 503                         0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
 504
 505                         /* IDSEL 0x11 func 5 - PCI slot 1 */
 506                         0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
 507                         0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
 508                         0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
 509                         0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
 510
 511                         /* IDSEL 0x11 func 6 - PCI slot 1 */
 512                         0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
 513                         0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
 514                         0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
 515                         0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
 516
 517                         /* IDSEL 0x11 func 7 - PCI slot 1 */
 518                         0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
 519                         0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
 520                         0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
 521                         0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
 522
 523                         /* IDSEL 0x12 func 0 - PCI slot 2 */
 524                         0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
 525                         0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
 526                         0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
 527                         0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
 528
 529                         /* IDSEL 0x12 func 1 - PCI slot 2 */
 530                         0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
 531                         0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
 532                         0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
 533                         0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
 534
 535                         /* IDSEL 0x12 func 2 - PCI slot 2 */
 536                         0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
 537                         0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
 538                         0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
 539                         0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
 540
 541                         /* IDSEL 0x12 func 3 - PCI slot 2 */
 542                         0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
 543                         0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
 544                         0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
 545                         0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
 546
 547                         /* IDSEL 0x12 func 4 - PCI slot 2 */
 548                         0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
 549                         0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
 550                         0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
 551                         0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
 552
 553                         /* IDSEL 0x12 func 5 - PCI slot 2 */
 554                         0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
 555                         0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
 556                         0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
 557                         0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
 558
 559                         /* IDSEL 0x12 func 6 - PCI slot 2 */
 560                         0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
 561                         0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
 562                         0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
 563                         0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
 564
 565                         /* IDSEL 0x12 func 7 - PCI slot 2 */
 566                         0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
 567                         0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
 568                         0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
 569                         0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
 570
 571                         // IDSEL 0x1c  USB
 572                         0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
 573                         0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
 574                         0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
 575                         0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
 576
 577                         // IDSEL 0x1d  Audio
 578                         0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 579
 580                         // IDSEL 0x1e Legacy
 581                         0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
 582                         0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 583
 584                         // IDSEL 0x1f IDE/SATA
 585                         0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
 586                         0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
 587
 588                         >;
 589
 590                 pcie@0 {
 591                         reg = <0x0 0x0 0x0 0x0 0x0>;
 592                         #size-cells = <2>;
 593                         #address-cells = <3>;
 594                         device_type = "pci";
 595                         ranges = <0x2000000 0x0 0x80000000
 596                                   0x2000000 0x0 0x80000000
 597                                   0x0 0x20000000
 598
 599                                   0x1000000 0x0 0x0
 600                                   0x1000000 0x0 0x0
 601                                   0x0 0x100000>;
 602                         uli1575@0 {
 603                                 reg = <0x0 0x0 0x0 0x0 0x0>;
 604                                 #size-cells = <2>;
 605                                 #address-cells = <3>;
 606                                 ranges = <0x2000000 0x0 0x80000000
 607                                           0x2000000 0x0 0x80000000
 608                                           0x0 0x20000000
 609
 610                                           0x1000000 0x0 0x0
 611                                           0x1000000 0x0 0x0
 612                                           0x0 0x100000>;
 613                                 isa@1e {
 614                                         device_type = "isa";
 615                                         #interrupt-cells = <2>;
 616                                         #size-cells = <1>;
 617                                         #address-cells = <2>;
 618                                         reg = <0xf000 0x0 0x0 0x0 0x0>;
 619                                         ranges = <0x1 0x0 0x1000000 0x0 0x0
 620                                                   0x1000>;
 621                                         interrupt-parent = <&i8259>;
 622
 623                                         i8259: interrupt-controller@20 {
 624                                                 reg = <0x1 0x20 0x2
 625                                                        0x1 0xa0 0x2
 626                                                        0x1 0x4d0 0x2>;
 627                                                 interrupt-controller;
 628                                                 device_type = "interrupt-controller";
 629                                                 #address-cells = <0>;
 630                                                 #interrupt-cells = <2>;
 631                                                 compatible = "chrp,iic";
 632                                                 interrupts = <9 2>;
 633                                                 interrupt-parent = <&mpic>;
 634                                         };
 635
 636                                         i8042@60 {
 637                                                 #size-cells = <0>;
 638                                                 #address-cells = <1>;
 639                                                 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
 640                                                 interrupts = <1 3 12 3>;
 641                                                 interrupt-parent =
 642                                                         <&i8259>;
 643
 644                                                 keyboard@0 {
 645                                                         reg = <0x0>;
 646                                                         compatible = "pnpPNP,303";
 647                                                 };
 648
 649                                                 mouse@1 {
 650                                                         reg = <0x1>;
 651                                                         compatible = "pnpPNP,f03";
 652                                                 };
 653                                         };
 654
 655                                         rtc@70 {
 656                                                 compatible = "pnpPNP,b00";
 657                                                 reg = <0x1 0x70 0x2>;
 658                                         };
 659
 660                                         gpio@400 {
 661                                                 reg = <0x1 0x400 0x80>;
 662                                         };
 663                                 };
 664                         };
 665                 };
 666
 667         };
 668
 669         pci1: pcie@ffe09000 {
 670                 cell-index = <1>;
 671                 compatible = "fsl,mpc8548-pcie";
 672                 device_type = "pci";
 673                 #interrupt-cells = <1>;
 674                 #size-cells = <2>;
 675                 #address-cells = <3>;
 676                 reg = <0 0xffe09000 0 0x1000>;
 677                 bus-range = <0 255>;
 678                 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
 679                           0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>;
 680                 clock-frequency = <33333333>;
 681                 interrupt-parent = <&mpic>;
 682                 interrupts = <26 2>;
 683                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 684                 interrupt-map = <
 685                         /* IDSEL 0x0 */
 686                         0000 0x0 0x0 0x1 &mpic 0x4 0x1
 687                         0000 0x0 0x0 0x2 &mpic 0x5 0x1
 688                         0000 0x0 0x0 0x3 &mpic 0x6 0x1
 689                         0000 0x0 0x0 0x4 &mpic 0x7 0x1
 690                         >;
 691                 pcie@0 {
 692                         reg = <0x0 0x0 0x0 0x0 0x0>;
 693                         #size-cells = <2>;
 694                         #address-cells = <3>;
 695                         device_type = "pci";
 696                         ranges = <0x2000000 0x0 0xa0000000
 697                                   0x2000000 0x0 0xa0000000
 698                                   0x0 0x20000000
 699
 700                                   0x1000000 0x0 0x0
 701                                   0x1000000 0x0 0x0
 702                                   0x0 0x100000>;
 703                 };
 704         };
 705
 706         pci2: pcie@ffe0a000 {
 707                 cell-index = <2>;
 708                 compatible = "fsl,mpc8548-pcie";
 709                 device_type = "pci";
 710                 #interrupt-cells = <1>;
 711                 #size-cells = <2>;
 712                 #address-cells = <3>;
 713                 reg = <0 0xffe0a000 0 0x1000>;
 714                 bus-range = <0 255>;
 715                 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
 716                           0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>;
 717                 clock-frequency = <33333333>;
 718                 interrupt-parent = <&mpic>;
 719                 interrupts = <27 2>;
 720                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 721                 interrupt-map = <
 722                         /* IDSEL 0x0 */
 723                         0000 0x0 0x0 0x1 &mpic 0x0 0x1
 724                         0000 0x0 0x0 0x2 &mpic 0x1 0x1
 725                         0000 0x0 0x0 0x3 &mpic 0x2 0x1
 726                         0000 0x0 0x0 0x4 &mpic 0x3 0x1
 727                         >;
 728                 pcie@0 {
 729                         reg = <0x0 0x0 0x0 0x0 0x0>;
 730                         #size-cells = <2>;
 731                         #address-cells = <3>;
 732                         device_type = "pci";
 733                         ranges = <0x2000000 0x0 0xc0000000
 734                                   0x2000000 0x0 0xc0000000
 735                                   0x0 0x20000000
 736
 737                                   0x1000000 0x0 0x0
 738                                   0x1000000 0x0 0x0
 739                                   0x0 0x100000>;
 740                 };
 741         };
 742 };