2 * MPC8572 DS Device Tree Source
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
14 model = "fsl,MPC8572DS";
15 compatible = "fsl,MPC8572DS";
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 timebase-frequency = <0>;
44 clock-frequency = <0>;
50 d-cache-line-size = <32>; // 32 bytes
51 i-cache-line-size = <32>; // 32 bytes
52 d-cache-size = <0x8000>; // L1, 32K
53 i-cache-size = <0x8000>; // L1, 32K
54 timebase-frequency = <0>;
56 clock-frequency = <0>;
61 device_type = "memory";
62 reg = <0x0 0x0>; // Filled by U-Boot
69 ranges = <0x0 0xffe00000 0x100000>;
70 reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
71 bus-frequency = <0>; // Filled out by uboot.
73 memory-controller@2000 {
74 compatible = "fsl,mpc8572-memory-controller";
75 reg = <0x2000 0x1000>;
76 interrupt-parent = <&mpic>;
80 memory-controller@6000 {
81 compatible = "fsl,mpc8572-memory-controller";
82 reg = <0x6000 0x1000>;
83 interrupt-parent = <&mpic>;
87 l2-cache-controller@20000 {
88 compatible = "fsl,mpc8572-l2-cache-controller";
89 reg = <0x20000 0x1000>;
90 cache-line-size = <32>; // 32 bytes
91 cache-size = <0x80000>; // L2, 512K
92 interrupt-parent = <&mpic>;
100 compatible = "fsl-i2c";
101 reg = <0x3000 0x100>;
103 interrupt-parent = <&mpic>;
108 #address-cells = <1>;
111 compatible = "fsl-i2c";
112 reg = <0x3100 0x100>;
114 interrupt-parent = <&mpic>;
119 #address-cells = <1>;
121 compatible = "fsl,gianfar-mdio";
122 reg = <0x24520 0x20>;
124 phy0: ethernet-phy@0 {
125 interrupt-parent = <&mpic>;
129 phy1: ethernet-phy@1 {
130 interrupt-parent = <&mpic>;
134 phy2: ethernet-phy@2 {
135 interrupt-parent = <&mpic>;
139 phy3: ethernet-phy@3 {
140 interrupt-parent = <&mpic>;
146 enet0: ethernet@24000 {
148 device_type = "network";
150 compatible = "gianfar";
151 reg = <0x24000 0x1000>;
152 local-mac-address = [ 00 00 00 00 00 00 ];
153 interrupts = <29 2 30 2 34 2>;
154 interrupt-parent = <&mpic>;
155 phy-handle = <&phy0>;
156 phy-connection-type = "rgmii-id";
159 enet1: ethernet@25000 {
161 device_type = "network";
163 compatible = "gianfar";
164 reg = <0x25000 0x1000>;
165 local-mac-address = [ 00 00 00 00 00 00 ];
166 interrupts = <35 2 36 2 40 2>;
167 interrupt-parent = <&mpic>;
168 phy-handle = <&phy1>;
169 phy-connection-type = "rgmii-id";
172 enet2: ethernet@26000 {
174 device_type = "network";
176 compatible = "gianfar";
177 reg = <0x26000 0x1000>;
178 local-mac-address = [ 00 00 00 00 00 00 ];
179 interrupts = <31 2 32 2 33 2>;
180 interrupt-parent = <&mpic>;
181 phy-handle = <&phy2>;
182 phy-connection-type = "rgmii-id";
185 enet3: ethernet@27000 {
187 device_type = "network";
189 compatible = "gianfar";
190 reg = <0x27000 0x1000>;
191 local-mac-address = [ 00 00 00 00 00 00 ];
192 interrupts = <37 2 38 2 39 2>;
193 interrupt-parent = <&mpic>;
194 phy-handle = <&phy3>;
195 phy-connection-type = "rgmii-id";
198 serial0: serial@4500 {
200 device_type = "serial";
201 compatible = "ns16550";
202 reg = <0x4500 0x100>;
203 clock-frequency = <0>;
205 interrupt-parent = <&mpic>;
208 serial1: serial@4600 {
210 device_type = "serial";
211 compatible = "ns16550";
212 reg = <0x4600 0x100>;
213 clock-frequency = <0>;
215 interrupt-parent = <&mpic>;
218 global-utilities@e0000 { //global utilities block
219 compatible = "fsl,mpc8572-guts";
220 reg = <0xe0000 0x1000>;
225 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
226 reg = <0x41600 0x80>;
227 msi-available-ranges = <0 0x100>;
237 interrupt-parent = <&mpic>;
241 interrupt-controller;
242 #address-cells = <0>;
243 #interrupt-cells = <2>;
244 reg = <0x40000 0x40000>;
245 compatible = "chrp,open-pic";
246 device_type = "open-pic";
250 pci0: pcie@ffe08000 {
252 compatible = "fsl,mpc8548-pcie";
254 #interrupt-cells = <1>;
256 #address-cells = <3>;
257 reg = <0xffe08000 0x1000>;
259 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
260 0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
261 clock-frequency = <33333333>;
262 interrupt-parent = <&mpic>;
264 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
266 /* IDSEL 0x11 func 0 - PCI slot 1 */
267 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
268 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
269 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
270 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
272 /* IDSEL 0x11 func 1 - PCI slot 1 */
273 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
274 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
275 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
276 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
278 /* IDSEL 0x11 func 2 - PCI slot 1 */
279 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
280 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
281 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
282 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
284 /* IDSEL 0x11 func 3 - PCI slot 1 */
285 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
286 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
287 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
288 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
290 /* IDSEL 0x11 func 4 - PCI slot 1 */
291 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
292 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
293 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
294 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
296 /* IDSEL 0x11 func 5 - PCI slot 1 */
297 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
298 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
299 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
300 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
302 /* IDSEL 0x11 func 6 - PCI slot 1 */
303 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
304 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
305 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
306 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
308 /* IDSEL 0x11 func 7 - PCI slot 1 */
309 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
310 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
311 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
312 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
314 /* IDSEL 0x12 func 0 - PCI slot 2 */
315 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
316 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
317 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
318 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
320 /* IDSEL 0x12 func 1 - PCI slot 2 */
321 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
322 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
323 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
324 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
326 /* IDSEL 0x12 func 2 - PCI slot 2 */
327 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
328 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
329 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
330 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
332 /* IDSEL 0x12 func 3 - PCI slot 2 */
333 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
334 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
335 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
336 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
338 /* IDSEL 0x12 func 4 - PCI slot 2 */
339 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
340 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
341 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
342 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
344 /* IDSEL 0x12 func 5 - PCI slot 2 */
345 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
346 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
347 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
348 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
350 /* IDSEL 0x12 func 6 - PCI slot 2 */
351 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
352 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
353 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
354 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
356 /* IDSEL 0x12 func 7 - PCI slot 2 */
357 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
358 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
359 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
360 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
363 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
364 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
365 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
366 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
369 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
372 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
373 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
375 // IDSEL 0x1f IDE/SATA
376 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
377 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
382 reg = <0x0 0x0 0x0 0x0 0x0>;
384 #address-cells = <3>;
386 ranges = <0x2000000 0x0 0x80000000
387 0x2000000 0x0 0x80000000
394 reg = <0x0 0x0 0x0 0x0 0x0>;
396 #address-cells = <3>;
397 ranges = <0x2000000 0x0 0x80000000
398 0x2000000 0x0 0x80000000
406 #interrupt-cells = <2>;
408 #address-cells = <2>;
409 reg = <0xf000 0x0 0x0 0x0 0x0>;
410 ranges = <0x1 0x0 0x1000000 0x0 0x0
412 interrupt-parent = <&i8259>;
414 i8259: interrupt-controller@20 {
418 interrupt-controller;
419 device_type = "interrupt-controller";
420 #address-cells = <0>;
421 #interrupt-cells = <2>;
422 compatible = "chrp,iic";
424 interrupt-parent = <&mpic>;
429 #address-cells = <1>;
430 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
431 interrupts = <1 3 12 3>;
437 compatible = "pnpPNP,303";
442 compatible = "pnpPNP,f03";
447 compatible = "pnpPNP,b00";
448 reg = <0x1 0x70 0x2>;
452 reg = <0x1 0x400 0x80>;
460 pci1: pcie@ffe09000 {
462 compatible = "fsl,mpc8548-pcie";
464 #interrupt-cells = <1>;
466 #address-cells = <3>;
467 reg = <0xffe09000 0x1000>;
469 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
470 0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
471 clock-frequency = <33333333>;
472 interrupt-parent = <&mpic>;
474 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
477 0000 0x0 0x0 0x1 &mpic 0x4 0x1
478 0000 0x0 0x0 0x2 &mpic 0x5 0x1
479 0000 0x0 0x0 0x3 &mpic 0x6 0x1
480 0000 0x0 0x0 0x4 &mpic 0x7 0x1
483 reg = <0x0 0x0 0x0 0x0 0x0>;
485 #address-cells = <3>;
487 ranges = <0x2000000 0x0 0xa0000000
488 0x2000000 0x0 0xa0000000
497 pci2: pcie@ffe0a000 {
499 compatible = "fsl,mpc8548-pcie";
501 #interrupt-cells = <1>;
503 #address-cells = <3>;
504 reg = <0xffe0a000 0x1000>;
506 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
507 0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
508 clock-frequency = <33333333>;
509 interrupt-parent = <&mpic>;
511 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
514 0000 0x0 0x0 0x1 &mpic 0x0 0x1
515 0000 0x0 0x0 0x2 &mpic 0x1 0x1
516 0000 0x0 0x0 0x3 &mpic 0x2 0x1
517 0000 0x0 0x0 0x4 &mpic 0x3 0x1
520 reg = <0x0 0x0 0x0 0x0 0x0>;
522 #address-cells = <3>;
524 ranges = <0x2000000 0x0 0xc0000000
525 0x2000000 0x0 0xc0000000