2 * MPC8555 CDS Device Tree Source
4 * Copyright 2006 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 compatible = "MPC8555CDS", "MPC85xxCDS";
26 d-cache-line-size = <20>; // 32 bytes
27 i-cache-line-size = <20>; // 32 bytes
28 d-cache-size = <8000>; // L1, 32K
29 i-cache-size = <8000>; // L1, 32K
30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // 166 MHz
32 clock-frequency = <0>; // 825 MHz, from uboot
37 device_type = "memory";
38 reg = <00000000 08000000>; // 128M at 0x0
45 ranges = <0 e0000000 00100000>;
46 reg = <e0000000 00001000>; // CCSRBAR 1M
49 memory-controller@2000 {
50 compatible = "fsl,8555-memory-controller";
52 interrupt-parent = <&mpic>;
56 l2-cache-controller@20000 {
57 compatible = "fsl,8555-l2-cache-controller";
59 cache-line-size = <20>; // 32 bytes
60 cache-size = <40000>; // L2, 256K
61 interrupt-parent = <&mpic>;
69 compatible = "fsl-i2c";
72 interrupt-parent = <&mpic>;
80 compatible = "gianfar";
82 phy0: ethernet-phy@0 {
83 interrupt-parent = <&mpic>;
86 device_type = "ethernet-phy";
88 phy1: ethernet-phy@1 {
89 interrupt-parent = <&mpic>;
92 device_type = "ethernet-phy";
99 device_type = "network";
101 compatible = "gianfar";
103 local-mac-address = [ 00 00 00 00 00 00 ];
104 interrupts = <1d 2 1e 2 22 2>;
105 interrupt-parent = <&mpic>;
106 phy-handle = <&phy0>;
110 #address-cells = <1>;
112 device_type = "network";
114 compatible = "gianfar";
116 local-mac-address = [ 00 00 00 00 00 00 ];
117 interrupts = <23 2 24 2 28 2>;
118 interrupt-parent = <&mpic>;
119 phy-handle = <&phy1>;
123 device_type = "serial";
124 compatible = "ns16550";
125 reg = <4500 100>; // reg base, size
126 clock-frequency = <0>; // should we fill in in uboot?
128 interrupt-parent = <&mpic>;
132 device_type = "serial";
133 compatible = "ns16550";
134 reg = <4600 100>; // reg base, size
135 clock-frequency = <0>; // should we fill in in uboot?
137 interrupt-parent = <&mpic>;
141 clock-frequency = <0>;
142 interrupt-controller;
143 #address-cells = <0>;
144 #interrupt-cells = <2>;
146 compatible = "chrp,open-pic";
147 device_type = "open-pic";
152 #address-cells = <1>;
154 compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
159 #address-cells = <1>;
161 ranges = <0 80000 10000>;
164 compatible = "fsl,cpm-muram-data";
165 reg = <0 2000 9000 1000>;
170 compatible = "fsl,mpc8555-brg",
173 reg = <919f0 10 915f0 10>;
177 interrupt-controller;
178 #address-cells = <0>;
179 #interrupt-cells = <2>;
181 interrupt-parent = <&mpic>;
183 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
189 interrupt-map-mask = <1f800 0 0 7>;
193 08000 0 0 1 &mpic 0 1
194 08000 0 0 2 &mpic 1 1
195 08000 0 0 3 &mpic 2 1
196 08000 0 0 4 &mpic 3 1
199 08800 0 0 1 &mpic 0 1
200 08800 0 0 2 &mpic 1 1
201 08800 0 0 3 &mpic 2 1
202 08800 0 0 4 &mpic 3 1
204 /* IDSEL 0x12 (Slot 1) */
205 09000 0 0 1 &mpic 0 1
206 09000 0 0 2 &mpic 1 1
207 09000 0 0 3 &mpic 2 1
208 09000 0 0 4 &mpic 3 1
210 /* IDSEL 0x13 (Slot 2) */
211 09800 0 0 1 &mpic 1 1
212 09800 0 0 2 &mpic 2 1
213 09800 0 0 3 &mpic 3 1
214 09800 0 0 4 &mpic 0 1
216 /* IDSEL 0x14 (Slot 3) */
217 0a000 0 0 1 &mpic 2 1
218 0a000 0 0 2 &mpic 3 1
219 0a000 0 0 3 &mpic 0 1
220 0a000 0 0 4 &mpic 1 1
222 /* IDSEL 0x15 (Slot 4) */
223 0a800 0 0 1 &mpic 3 1
224 0a800 0 0 2 &mpic 0 1
225 0a800 0 0 3 &mpic 1 1
226 0a800 0 0 4 &mpic 2 1
228 /* Bus 1 (Tundra Bridge) */
229 /* IDSEL 0x12 (ISA bridge) */
230 19000 0 0 1 &mpic 0 1
231 19000 0 0 2 &mpic 1 1
232 19000 0 0 3 &mpic 2 1
233 19000 0 0 4 &mpic 3 1>;
234 interrupt-parent = <&mpic>;
237 ranges = <02000000 0 80000000 80000000 0 20000000
238 01000000 0 00000000 e2000000 0 00100000>;
239 clock-frequency = <3f940aa>;
240 #interrupt-cells = <1>;
242 #address-cells = <3>;
243 reg = <e0008000 1000>;
244 compatible = "fsl,mpc8540-pci";
248 interrupt-controller;
249 device_type = "interrupt-controller";
250 reg = <19000 0 0 0 1>;
251 #address-cells = <0>;
252 #interrupt-cells = <2>;
253 compatible = "chrp,iic";
255 interrupt-parent = <&pci1>;
260 interrupt-map-mask = <f800 0 0 7>;
267 a800 0 0 4 &mpic b 1>;
268 interrupt-parent = <&mpic>;
271 ranges = <02000000 0 a0000000 a0000000 0 20000000
272 01000000 0 00000000 e3000000 0 00100000>;
273 clock-frequency = <3f940aa>;
274 #interrupt-cells = <1>;
276 #address-cells = <3>;
277 reg = <e0009000 1000>;
278 compatible = "fsl,mpc8540-pci";