arch/powerpc/boot/dts/mpc8544ds.dts

   1 /*
   2  * MPC8544 DS Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 / {
  13         model = "MPC8544DS";
  14         compatible = "MPC8544DS", "MPC85xxDS";
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         cpus {
  19                 #cpus = <1>;
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 PowerPC,8544@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         d-cache-line-size = <20>;       // 32 bytes
  27                         i-cache-line-size = <20>;       // 32 bytes
  28                         d-cache-size = <8000>;          // L1, 32K
  29                         i-cache-size = <8000>;          // L1, 32K
  30                         timebase-frequency = <0>;
  31                         bus-frequency = <0>;
  32                         clock-frequency = <0>;
  33                 };
  34         };
  35
  36         memory {
  37                 device_type = "memory";
  38                 reg = <00000000 00000000>;      // Filled by U-Boot
  39         };
  40
  41         soc8544@e0000000 {
  42                 #address-cells = <1>;
  43                 #size-cells = <1>;
  44                 device_type = "soc";
  45
  46                 ranges = <00000000 e0000000 00100000>;
  47                 reg = <e0000000 00001000>;      // CCSRBAR 1M
  48                 bus-frequency = <0>;            // Filled out by uboot.
  49
  50                 memory-controller@2000 {
  51                         compatible = "fsl,8544-memory-controller";
  52                         reg = <2000 1000>;
  53                         interrupt-parent = <&mpic>;
  54                         interrupts = <12 2>;
  55                 };
  56
  57                 l2-cache-controller@20000 {
  58                         compatible = "fsl,8544-l2-cache-controller";
  59                         reg = <20000 1000>;
  60                         cache-line-size = <20>; // 32 bytes
  61                         cache-size = <40000>;   // L2, 256K
  62                         interrupt-parent = <&mpic>;
  63                         interrupts = <10 2>;
  64                 };
  65
  66                 i2c@3000 {
  67                         #address-cells = <1>;
  68                         #size-cells = <0>;
  69                         cell-index = <0>;
  70                         compatible = "fsl-i2c";
  71                         reg = <3000 100>;
  72                         interrupts = <2b 2>;
  73                         interrupt-parent = <&mpic>;
  74                         dfsrr;
  75                 };
  76
  77                 i2c@3100 {
  78                         #address-cells = <1>;
  79                         #size-cells = <0>;
  80                         cell-index = <1>;
  81                         compatible = "fsl-i2c";
  82                         reg = <3100 100>;
  83                         interrupts = <2b 2>;
  84                         interrupt-parent = <&mpic>;
  85                         dfsrr;
  86                 };
  87
  88                 mdio@24520 {
  89                         #address-cells = <1>;
  90                         #size-cells = <0>;
  91                         device_type = "mdio";
  92                         compatible = "gianfar";
  93                         reg = <24520 20>;
  94                         phy0: ethernet-phy@0 {
  95                                 interrupt-parent = <&mpic>;
  96                                 interrupts = <a 1>;
  97                                 reg = <0>;
  98                                 device_type = "ethernet-phy";
  99                         };
 100                         phy1: ethernet-phy@1 {
 101                                 interrupt-parent = <&mpic>;
 102                                 interrupts = <a 1>;
 103                                 reg = <1>;
 104                                 device_type = "ethernet-phy";
 105                         };
 106                 };
 107
 108                 ethernet@24000 {
 109                         #address-cells = <1>;
 110                         #size-cells = <0>;
 111                         device_type = "network";
 112                         model = "TSEC";
 113                         compatible = "gianfar";
 114                         reg = <24000 1000>;
 115                         local-mac-address = [ 00 00 00 00 00 00 ];
 116                         interrupts = <1d 2 1e 2 22 2>;
 117                         interrupt-parent = <&mpic>;
 118                         phy-handle = <&phy0>;
 119                         phy-connection-type = "rgmii-id";
 120                 };
 121
 122                 ethernet@26000 {
 123                         #address-cells = <1>;
 124                         #size-cells = <0>;
 125                         device_type = "network";
 126                         model = "TSEC";
 127                         compatible = "gianfar";
 128                         reg = <26000 1000>;
 129                         local-mac-address = [ 00 00 00 00 00 00 ];
 130                         interrupts = <1f 2 20 2 21 2>;
 131                         interrupt-parent = <&mpic>;
 132                         phy-handle = <&phy1>;
 133                         phy-connection-type = "rgmii-id";
 134                 };
 135
 136                 serial@4500 {
 137                         device_type = "serial";
 138                         compatible = "ns16550";
 139                         reg = <4500 100>;
 140                         clock-frequency = <0>;
 141                         interrupts = <2a 2>;
 142                         interrupt-parent = <&mpic>;
 143                 };
 144
 145                 serial@4600 {
 146                         device_type = "serial";
 147                         compatible = "ns16550";
 148                         reg = <4600 100>;
 149                         clock-frequency = <0>;
 150                         interrupts = <2a 2>;
 151                         interrupt-parent = <&mpic>;
 152                 };
 153
 154                 global-utilities@e0000 {        //global utilities block
 155                         compatible = "fsl,mpc8548-guts";
 156                         reg = <e0000 1000>;
 157                         fsl,has-rstcr;
 158                 };
 159
 160                 mpic: pic@40000 {
 161                         clock-frequency = <0>;
 162                         interrupt-controller;
 163                         #address-cells = <0>;
 164                         #interrupt-cells = <2>;
 165                         reg = <40000 40000>;
 166                         compatible = "chrp,open-pic";
 167                         device_type = "open-pic";
 168                         big-endian;
 169                 };
 170         };
 171
 172         pci@e0008000 {
 173                 compatible = "fsl,mpc8540-pci";
 174                 device_type = "pci";
 175                 interrupt-map-mask = <f800 0 0 7>;
 176                 interrupt-map = <
 177
 178                         /* IDSEL 0x11 J17 Slot 1 */
 179                         8800 0 0 1 &mpic 2 1
 180                         8800 0 0 2 &mpic 3 1
 181                         8800 0 0 3 &mpic 4 1
 182                         8800 0 0 4 &mpic 1 1
 183
 184                         /* IDSEL 0x12 J16 Slot 2 */
 185
 186                         9000 0 0 1 &mpic 3 1
 187                         9000 0 0 2 &mpic 4 1
 188                         9000 0 0 3 &mpic 2 1
 189                         9000 0 0 4 &mpic 1 1>;
 190
 191                 interrupt-parent = <&mpic>;
 192                 interrupts = <18 2>;
 193                 bus-range = <0 ff>;
 194                 ranges = <02000000 0 c0000000 c0000000 0 20000000
 195                           01000000 0 00000000 e1000000 0 00010000>;
 196                 clock-frequency = <3f940aa>;
 197                 #interrupt-cells = <1>;
 198                 #size-cells = <2>;
 199                 #address-cells = <3>;
 200                 reg = <e0008000 1000>;
 201         };
 202
 203         pcie@e0009000 {
 204                 compatible = "fsl,mpc8548-pcie";
 205                 device_type = "pci";
 206                 #interrupt-cells = <1>;
 207                 #size-cells = <2>;
 208                 #address-cells = <3>;
 209                 reg = <e0009000 1000>;
 210                 bus-range = <0 ff>;
 211                 ranges = <02000000 0 80000000 80000000 0 20000000
 212                           01000000 0 00000000 e1010000 0 00010000>;
 213                 clock-frequency = <1fca055>;
 214                 interrupt-parent = <&mpic>;
 215                 interrupts = <1a 2>;
 216                 interrupt-map-mask = <f800 0 0 7>;
 217                 interrupt-map = <
 218                         /* IDSEL 0x0 */
 219                         0000 0 0 1 &mpic 4 1
 220                         0000 0 0 2 &mpic 5 1
 221                         0000 0 0 3 &mpic 6 1
 222                         0000 0 0 4 &mpic 7 1
 223                         >;
 224                 pcie@0 {
 225                         reg = <0 0 0 0 0>;
 226                         #size-cells = <2>;
 227                         #address-cells = <3>;
 228                         device_type = "pci";
 229                         ranges = <02000000 0 80000000
 230                                   02000000 0 80000000
 231                                   0 20000000
 232
 233                                   01000000 0 00000000
 234                                   01000000 0 00000000
 235                                   0 00010000>;
 236                 };
 237         };
 238
 239         pcie@e000a000 {
 240                 compatible = "fsl,mpc8548-pcie";
 241                 device_type = "pci";
 242                 #interrupt-cells = <1>;
 243                 #size-cells = <2>;
 244                 #address-cells = <3>;
 245                 reg = <e000a000 1000>;
 246                 bus-range = <0 ff>;
 247                 ranges = <02000000 0 a0000000 a0000000 0 10000000
 248                           01000000 0 00000000 e1020000 0 00010000>;
 249                 clock-frequency = <1fca055>;
 250                 interrupt-parent = <&mpic>;
 251                 interrupts = <19 2>;
 252                 interrupt-map-mask = <f800 0 0 7>;
 253                 interrupt-map = <
 254                         /* IDSEL 0x0 */
 255                         0000 0 0 1 &mpic 0 1
 256                         0000 0 0 2 &mpic 1 1
 257                         0000 0 0 3 &mpic 2 1
 258                         0000 0 0 4 &mpic 3 1
 259                         >;
 260                 pcie@0 {
 261                         reg = <0 0 0 0 0>;
 262                         #size-cells = <2>;
 263                         #address-cells = <3>;
 264                         device_type = "pci";
 265                         ranges = <02000000 0 a0000000
 266                                   02000000 0 a0000000
 267                                   0 10000000
 268
 269                                   01000000 0 00000000
 270                                   01000000 0 00000000
 271                                   0 00010000>;
 272                 };
 273         };
 274
 275         pcie@e000b000 {
 276                 compatible = "fsl,mpc8548-pcie";
 277                 device_type = "pci";
 278                 #interrupt-cells = <1>;
 279                 #size-cells = <2>;
 280                 #address-cells = <3>;
 281                 reg = <e000b000 1000>;
 282                 bus-range = <0 ff>;
 283                 ranges = <02000000 0 b0000000 b0000000 0 00100000
 284                           01000000 0 00000000 b0100000 0 00100000>;
 285                 clock-frequency = <1fca055>;
 286                 interrupt-parent = <&mpic>;
 287                 interrupts = <1b 2>;
 288                 interrupt-map-mask = <ff00 0 0 1>;
 289                 interrupt-map = <
 290                         // IDSEL 0x1c  USB
 291                         e000 0 0 1 &i8259 c 2
 292                         e100 0 0 1 &i8259 9 2
 293                         e200 0 0 1 &i8259 a 2
 294                         e300 0 0 1 &i8259 b 2
 295
 296                         // IDSEL 0x1d  Audio
 297                         e800 0 0 1 &i8259 6 2
 298
 299                         // IDSEL 0x1e Legacy
 300                         f000 0 0 1 &i8259 7 2
 301                         f100 0 0 1 &i8259 7 2
 302
 303                         // IDSEL 0x1f IDE/SATA
 304                         f800 0 0 1 &i8259 e 2
 305                         f900 0 0 1 &i8259 5 2
 306                 >;
 307
 308                 pcie@0 {
 309                         reg = <0 0 0 0 0>;
 310                         #size-cells = <2>;
 311                         #address-cells = <3>;
 312                         device_type = "pci";
 313                         ranges = <02000000 0 b0000000
 314                                   02000000 0 b0000000
 315                                   0 00100000
 316
 317                                   01000000 0 00000000
 318                                   01000000 0 00000000
 319                                   0 00100000>;
 320
 321                         uli1575@0 {
 322                                 reg = <0 0 0 0 0>;
 323                                 #size-cells = <2>;
 324                                 #address-cells = <3>;
 325                                 ranges = <02000000 0 b0000000
 326                                           02000000 0 b0000000
 327                                           0 00100000
 328
 329                                           01000000 0 00000000
 330                                           01000000 0 00000000
 331                                           0 00100000>;
 332                                 isa@1e {
 333                                         device_type = "isa";
 334                                         #interrupt-cells = <2>;
 335                                         #size-cells = <1>;
 336                                         #address-cells = <2>;
 337                                         reg = <f000 0 0 0 0>;
 338                                         ranges = <1 0
 339                                                   01000000 0 0
 340                                                   00001000>;
 341                                         interrupt-parent = <&i8259>;
 342
 343                                         i8259: interrupt-controller@20 {
 344                                                 reg = <1 20 2
 345                                                        1 a0 2
 346                                                        1 4d0 2>;
 347                                                 interrupt-controller;
 348                                                 device_type = "interrupt-controller";
 349                                                 #address-cells = <0>;
 350                                                 #interrupt-cells = <2>;
 351                                                 compatible = "chrp,iic";
 352                                                 interrupts = <9 2>;
 353                                                 interrupt-parent = <&mpic>;
 354                                         };
 355
 356                                         i8042@60 {
 357                                                 #size-cells = <0>;
 358                                                 #address-cells = <1>;
 359                                                 reg = <1 60 1 1 64 1>;
 360                                                 interrupts = <1 3 c 3>;
 361                                                 interrupt-parent = <&i8259>;
 362
 363                                                 keyboard@0 {
 364                                                         reg = <0>;
 365                                                         compatible = "pnpPNP,303";
 366                                                 };
 367
 368                                                 mouse@1 {
 369                                                         reg = <1>;
 370                                                         compatible = "pnpPNP,f03";
 371                                                 };
 372                                         };
 373
 374                                         rtc@70 {
 375                                                 compatible = "pnpPNP,b00";
 376                                                 reg = <1 70 2>;
 377                                         };
 378
 379                                         gpio@400 {
 380                                                 reg = <1 400 80>;
 381                                         };
 382                                 };
 383                         };
 384                 };
 385
 386         };
 387 };