arch/powerpc/boot/dts/mpc8544ds.dts

   1 /*
   2  * MPC8544 DS Device Tree Source
   3  *
   4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13 / {
  14         model = "MPC8544DS";
  15         compatible = "MPC8544DS", "MPC85xxDS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 ethernet0 = &enet0;
  21                 ethernet1 = &enet1;
  22                 serial0 = &serial0;
  23                 serial1 = &serial1;
  24                 pci0 = &pci0;
  25                 pci1 = &pci1;
  26                 pci2 = &pci2;
  27                 pci3 = &pci3;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 PowerPC,8544@0 {
  35                         device_type = "cpu";
  36                         reg = <0x0>;
  37                         d-cache-line-size = <32>;       // 32 bytes
  38                         i-cache-line-size = <32>;       // 32 bytes
  39                         d-cache-size = <0x8000>;                // L1, 32K
  40                         i-cache-size = <0x8000>;                // L1, 32K
  41                         timebase-frequency = <0>;
  42                         bus-frequency = <0>;
  43                         clock-frequency = <0>;
  44                 };
  45         };
  46
  47         memory {
  48                 device_type = "memory";
  49                 reg = <0x0 0x0>;        // Filled by U-Boot
  50         };
  51
  52         soc8544@e0000000 {
  53                 #address-cells = <1>;
  54                 #size-cells = <1>;
  55                 device_type = "soc";
  56
  57                 ranges = <0x0 0xe0000000 0x100000>;
  58                 reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
  59                 bus-frequency = <0>;            // Filled out by uboot.
  60
  61                 memory-controller@2000 {
  62                         compatible = "fsl,8544-memory-controller";
  63                         reg = <0x2000 0x1000>;
  64                         interrupt-parent = <&mpic>;
  65                         interrupts = <18 2>;
  66                 };
  67
  68                 l2-cache-controller@20000 {
  69                         compatible = "fsl,8544-l2-cache-controller";
  70                         reg = <0x20000 0x1000>;
  71                         cache-line-size = <32>; // 32 bytes
  72                         cache-size = <0x40000>; // L2, 256K
  73                         interrupt-parent = <&mpic>;
  74                         interrupts = <16 2>;
  75                 };
  76
  77                 i2c@3000 {
  78                         #address-cells = <1>;
  79                         #size-cells = <0>;
  80                         cell-index = <0>;
  81                         compatible = "fsl-i2c";
  82                         reg = <0x3000 0x100>;
  83                         interrupts = <43 2>;
  84                         interrupt-parent = <&mpic>;
  85                         dfsrr;
  86                 };
  87
  88                 i2c@3100 {
  89                         #address-cells = <1>;
  90                         #size-cells = <0>;
  91                         cell-index = <1>;
  92                         compatible = "fsl-i2c";
  93                         reg = <0x3100 0x100>;
  94                         interrupts = <43 2>;
  95                         interrupt-parent = <&mpic>;
  96                         dfsrr;
  97                 };
  98
  99                 mdio@24520 {
 100                         #address-cells = <1>;
 101                         #size-cells = <0>;
 102                         compatible = "fsl,gianfar-mdio";
 103                         reg = <0x24520 0x20>;
 104
 105                         phy0: ethernet-phy@0 {
 106                                 interrupt-parent = <&mpic>;
 107                                 interrupts = <10 1>;
 108                                 reg = <0x0>;
 109                                 device_type = "ethernet-phy";
 110                         };
 111                         phy1: ethernet-phy@1 {
 112                                 interrupt-parent = <&mpic>;
 113                                 interrupts = <10 1>;
 114                                 reg = <0x1>;
 115                                 device_type = "ethernet-phy";
 116                         };
 117                 };
 118
 119                 dma@21300 {
 120                         #address-cells = <1>;
 121                         #size-cells = <1>;
 122                         compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
 123                         reg = <0x21300 0x4>;
 124                         ranges = <0x0 0x21100 0x200>;
 125                         cell-index = <0>;
 126                         dma-channel@0 {
 127                                 compatible = "fsl,mpc8544-dma-channel",
 128                                                 "fsl,eloplus-dma-channel";
 129                                 reg = <0x0 0x80>;
 130                                 cell-index = <0>;
 131                                 interrupt-parent = <&mpic>;
 132                                 interrupts = <20 2>;
 133                         };
 134                         dma-channel@80 {
 135                                 compatible = "fsl,mpc8544-dma-channel",
 136                                                 "fsl,eloplus-dma-channel";
 137                                 reg = <0x80 0x80>;
 138                                 cell-index = <1>;
 139                                 interrupt-parent = <&mpic>;
 140                                 interrupts = <21 2>;
 141                         };
 142                         dma-channel@100 {
 143                                 compatible = "fsl,mpc8544-dma-channel",
 144                                                 "fsl,eloplus-dma-channel";
 145                                 reg = <0x100 0x80>;
 146                                 cell-index = <2>;
 147                                 interrupt-parent = <&mpic>;
 148                                 interrupts = <22 2>;
 149                         };
 150                         dma-channel@180 {
 151                                 compatible = "fsl,mpc8544-dma-channel",
 152                                                 "fsl,eloplus-dma-channel";
 153                                 reg = <0x180 0x80>;
 154                                 cell-index = <3>;
 155                                 interrupt-parent = <&mpic>;
 156                                 interrupts = <23 2>;
 157                         };
 158                 };
 159
 160                 enet0: ethernet@24000 {
 161                         cell-index = <0>;
 162                         device_type = "network";
 163                         model = "TSEC";
 164                         compatible = "gianfar";
 165                         reg = <0x24000 0x1000>;
 166                         local-mac-address = [ 00 00 00 00 00 00 ];
 167                         interrupts = <29 2 30 2 34 2>;
 168                         interrupt-parent = <&mpic>;
 169                         phy-handle = <&phy0>;
 170                         phy-connection-type = "rgmii-id";
 171                 };
 172
 173                 enet1: ethernet@26000 {
 174                         cell-index = <1>;
 175                         device_type = "network";
 176                         model = "TSEC";
 177                         compatible = "gianfar";
 178                         reg = <0x26000 0x1000>;
 179                         local-mac-address = [ 00 00 00 00 00 00 ];
 180                         interrupts = <31 2 32 2 33 2>;
 181                         interrupt-parent = <&mpic>;
 182                         phy-handle = <&phy1>;
 183                         phy-connection-type = "rgmii-id";
 184                 };
 185
 186                 serial0: serial@4500 {
 187                         cell-index = <0>;
 188                         device_type = "serial";
 189                         compatible = "ns16550";
 190                         reg = <0x4500 0x100>;
 191                         clock-frequency = <0>;
 192                         interrupts = <42 2>;
 193                         interrupt-parent = <&mpic>;
 194                 };
 195
 196                 serial1: serial@4600 {
 197                         cell-index = <1>;
 198                         device_type = "serial";
 199                         compatible = "ns16550";
 200                         reg = <0x4600 0x100>;
 201                         clock-frequency = <0>;
 202                         interrupts = <42 2>;
 203                         interrupt-parent = <&mpic>;
 204                 };
 205
 206                 global-utilities@e0000 {        //global utilities block
 207                         compatible = "fsl,mpc8548-guts";
 208                         reg = <0xe0000 0x1000>;
 209                         fsl,has-rstcr;
 210                 };
 211
 212                 mpic: pic@40000 {
 213                         clock-frequency = <0>;
 214                         interrupt-controller;
 215                         #address-cells = <0>;
 216                         #interrupt-cells = <2>;
 217                         reg = <0x40000 0x40000>;
 218                         compatible = "chrp,open-pic";
 219                         device_type = "open-pic";
 220                         big-endian;
 221                 };
 222         };
 223
 224         pci0: pci@e0008000 {
 225                 cell-index = <0>;
 226                 compatible = "fsl,mpc8540-pci";
 227                 device_type = "pci";
 228                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 229                 interrupt-map = <
 230
 231                         /* IDSEL 0x11 J17 Slot 1 */
 232                         0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
 233                         0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
 234                         0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
 235                         0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
 236
 237                         /* IDSEL 0x12 J16 Slot 2 */
 238
 239                         0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
 240                         0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
 241                         0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
 242                         0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
 243
 244                 interrupt-parent = <&mpic>;
 245                 interrupts = <24 2>;
 246                 bus-range = <0 255>;
 247                 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
 248                           0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
 249                 clock-frequency = <66666666>;
 250                 #interrupt-cells = <1>;
 251                 #size-cells = <2>;
 252                 #address-cells = <3>;
 253                 reg = <0xe0008000 0x1000>;
 254         };
 255
 256         pci1: pcie@e0009000 {
 257                 cell-index = <1>;
 258                 compatible = "fsl,mpc8548-pcie";
 259                 device_type = "pci";
 260                 #interrupt-cells = <1>;
 261                 #size-cells = <2>;
 262                 #address-cells = <3>;
 263                 reg = <0xe0009000 0x1000>;
 264                 bus-range = <0 255>;
 265                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 266                           0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
 267                 clock-frequency = <33333333>;
 268                 interrupt-parent = <&mpic>;
 269                 interrupts = <26 2>;
 270                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 271                 interrupt-map = <
 272                         /* IDSEL 0x0 */
 273                         0000 0x0 0x0 0x1 &mpic 0x4 0x1
 274                         0000 0x0 0x0 0x2 &mpic 0x5 0x1
 275                         0000 0x0 0x0 0x3 &mpic 0x6 0x1
 276                         0000 0x0 0x0 0x4 &mpic 0x7 0x1
 277                         >;
 278                 pcie@0 {
 279                         reg = <0x0 0x0 0x0 0x0 0x0>;
 280                         #size-cells = <2>;
 281                         #address-cells = <3>;
 282                         device_type = "pci";
 283                         ranges = <0x2000000 0x0 0x80000000
 284                                   0x2000000 0x0 0x80000000
 285                                   0x0 0x20000000
 286
 287                                   0x1000000 0x0 0x0
 288                                   0x1000000 0x0 0x0
 289                                   0x0 0x10000>;
 290                 };
 291         };
 292
 293         pci2: pcie@e000a000 {
 294                 cell-index = <2>;
 295                 compatible = "fsl,mpc8548-pcie";
 296                 device_type = "pci";
 297                 #interrupt-cells = <1>;
 298                 #size-cells = <2>;
 299                 #address-cells = <3>;
 300                 reg = <0xe000a000 0x1000>;
 301                 bus-range = <0 255>;
 302                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 303                           0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
 304                 clock-frequency = <33333333>;
 305                 interrupt-parent = <&mpic>;
 306                 interrupts = <25 2>;
 307                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 308                 interrupt-map = <
 309                         /* IDSEL 0x0 */
 310                         0000 0x0 0x0 0x1 &mpic 0x0 0x1
 311                         0000 0x0 0x0 0x2 &mpic 0x1 0x1
 312                         0000 0x0 0x0 0x3 &mpic 0x2 0x1
 313                         0000 0x0 0x0 0x4 &mpic 0x3 0x1
 314                         >;
 315                 pcie@0 {
 316                         reg = <0x0 0x0 0x0 0x0 0x0>;
 317                         #size-cells = <2>;
 318                         #address-cells = <3>;
 319                         device_type = "pci";
 320                         ranges = <0x2000000 0x0 0xa0000000
 321                                   0x2000000 0x0 0xa0000000
 322                                   0x0 0x10000000
 323
 324                                   0x1000000 0x0 0x0
 325                                   0x1000000 0x0 0x0
 326                                   0x0 0x10000>;
 327                 };
 328         };
 329
 330         pci3: pcie@e000b000 {
 331                 cell-index = <3>;
 332                 compatible = "fsl,mpc8548-pcie";
 333                 device_type = "pci";
 334                 #interrupt-cells = <1>;
 335                 #size-cells = <2>;
 336                 #address-cells = <3>;
 337                 reg = <0xe000b000 0x1000>;
 338                 bus-range = <0 255>;
 339                 ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
 340                           0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
 341                 clock-frequency = <33333333>;
 342                 interrupt-parent = <&mpic>;
 343                 interrupts = <27 2>;
 344                 interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
 345                 interrupt-map = <
 346                         // IDSEL 0x1c  USB
 347                         0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
 348                         0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
 349                         0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
 350                         0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
 351
 352                         // IDSEL 0x1d  Audio
 353                         0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 354
 355                         // IDSEL 0x1e Legacy
 356                         0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
 357                         0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 358
 359                         // IDSEL 0x1f IDE/SATA
 360                         0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
 361                         0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
 362                 >;
 363
 364                 pcie@0 {
 365                         reg = <0x0 0x0 0x0 0x0 0x0>;
 366                         #size-cells = <2>;
 367                         #address-cells = <3>;
 368                         device_type = "pci";
 369                         ranges = <0x2000000 0x0 0xb0000000
 370                                   0x2000000 0x0 0xb0000000
 371                                   0x0 0x100000
 372
 373                                   0x1000000 0x0 0x0
 374                                   0x1000000 0x0 0x0
 375                                   0x0 0x100000>;
 376
 377                         uli1575@0 {
 378                                 reg = <0x0 0x0 0x0 0x0 0x0>;
 379                                 #size-cells = <2>;
 380                                 #address-cells = <3>;
 381                                 ranges = <0x2000000 0x0 0xb0000000
 382                                           0x2000000 0x0 0xb0000000
 383                                           0x0 0x100000
 384
 385                                           0x1000000 0x0 0x0
 386                                           0x1000000 0x0 0x0
 387                                           0x0 0x100000>;
 388                                 isa@1e {
 389                                         device_type = "isa";
 390                                         #interrupt-cells = <2>;
 391                                         #size-cells = <1>;
 392                                         #address-cells = <2>;
 393                                         reg = <0xf000 0x0 0x0 0x0 0x0>;
 394                                         ranges = <0x1 0x0
 395                                                   0x1000000 0x0 0x0
 396                                                   0x1000>;
 397                                         interrupt-parent = <&i8259>;
 398
 399                                         i8259: interrupt-controller@20 {
 400                                                 reg = <0x1 0x20 0x2
 401                                                        0x1 0xa0 0x2
 402                                                        0x1 0x4d0 0x2>;
 403                                                 interrupt-controller;
 404                                                 device_type = "interrupt-controller";
 405                                                 #address-cells = <0>;
 406                                                 #interrupt-cells = <2>;
 407                                                 compatible = "chrp,iic";
 408                                                 interrupts = <9 2>;
 409                                                 interrupt-parent = <&mpic>;
 410                                         };
 411
 412                                         i8042@60 {
 413                                                 #size-cells = <0>;
 414                                                 #address-cells = <1>;
 415                                                 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
 416                                                 interrupts = <1 3 12 3>;
 417                                                 interrupt-parent = <&i8259>;
 418
 419                                                 keyboard@0 {
 420                                                         reg = <0x0>;
 421                                                         compatible = "pnpPNP,303";
 422                                                 };
 423
 424                                                 mouse@1 {
 425                                                         reg = <0x1>;
 426                                                         compatible = "pnpPNP,f03";
 427                                                 };
 428                                         };
 429
 430                                         rtc@70 {
 431                                                 compatible = "pnpPNP,b00";
 432                                                 reg = <0x1 0x70 0x2>;
 433                                         };
 434
 435                                         gpio@400 {
 436                                                 reg = <0x1 0x400 0x80>;
 437                                         };
 438                                 };
 439                         };
 440                 };
 441         };
 442 };