arch/powerpc/boot/dts/mpc8544ds.dts

   1 /*
   2  * MPC8544 DS Device Tree Source
   3  *
   4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13 / {
  14         model = "MPC8544DS";
  15         compatible = "MPC8544DS", "MPC85xxDS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 ethernet0 = &enet0;
  21                 ethernet1 = &enet1;
  22                 serial0 = &serial0;
  23                 serial1 = &serial1;
  24                 pci0 = &pci0;
  25                 pci1 = &pci1;
  26                 pci2 = &pci2;
  27                 pci3 = &pci3;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 PowerPC,8544@0 {
  35                         device_type = "cpu";
  36                         reg = <0x0>;
  37                         d-cache-line-size = <32>;       // 32 bytes
  38                         i-cache-line-size = <32>;       // 32 bytes
  39                         d-cache-size = <0x8000>;                // L1, 32K
  40                         i-cache-size = <0x8000>;                // L1, 32K
  41                         timebase-frequency = <0>;
  42                         bus-frequency = <0>;
  43                         clock-frequency = <0>;
  44                 };
  45         };
  46
  47         memory {
  48                 device_type = "memory";
  49                 reg = <0x0 0x0>;        // Filled by U-Boot
  50         };
  51
  52         soc8544@e0000000 {
  53                 #address-cells = <1>;
  54                 #size-cells = <1>;
  55                 device_type = "soc";
  56
  57                 ranges = <0x0 0xe0000000 0x100000>;
  58                 reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
  59                 bus-frequency = <0>;            // Filled out by uboot.
  60
  61                 memory-controller@2000 {
  62                         compatible = "fsl,8544-memory-controller";
  63                         reg = <0x2000 0x1000>;
  64                         interrupt-parent = <&mpic>;
  65                         interrupts = <18 2>;
  66                 };
  67
  68                 l2-cache-controller@20000 {
  69                         compatible = "fsl,8544-l2-cache-controller";
  70                         reg = <0x20000 0x1000>;
  71                         cache-line-size = <32>; // 32 bytes
  72                         cache-size = <0x40000>; // L2, 256K
  73                         interrupt-parent = <&mpic>;
  74                         interrupts = <16 2>;
  75                 };
  76
  77                 i2c@3000 {
  78                         #address-cells = <1>;
  79                         #size-cells = <0>;
  80                         cell-index = <0>;
  81                         compatible = "fsl-i2c";
  82                         reg = <0x3000 0x100>;
  83                         interrupts = <43 2>;
  84                         interrupt-parent = <&mpic>;
  85                         dfsrr;
  86                 };
  87
  88                 i2c@3100 {
  89                         #address-cells = <1>;
  90                         #size-cells = <0>;
  91                         cell-index = <1>;
  92                         compatible = "fsl-i2c";
  93                         reg = <0x3100 0x100>;
  94                         interrupts = <43 2>;
  95                         interrupt-parent = <&mpic>;
  96                         dfsrr;
  97                 };
  98
  99                 mdio@24520 {
 100                         #address-cells = <1>;
 101                         #size-cells = <0>;
 102                         compatible = "fsl,gianfar-mdio";
 103                         reg = <0x24520 0x20>;
 104
 105                         phy0: ethernet-phy@0 {
 106                                 interrupt-parent = <&mpic>;
 107                                 interrupts = <10 1>;
 108                                 reg = <0x0>;
 109                                 device_type = "ethernet-phy";
 110                         };
 111                         phy1: ethernet-phy@1 {
 112                                 interrupt-parent = <&mpic>;
 113                                 interrupts = <10 1>;
 114                                 reg = <0x1>;
 115                                 device_type = "ethernet-phy";
 116                         };
 117                 };
 118
 119                 dma@21300 {
 120                         #address-cells = <1>;
 121                         #size-cells = <1>;
 122                         compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
 123                         reg = <0x21300 0x4>;
 124                         ranges = <0x0 0x21100 0x200>;
 125                         cell-index = <0>;
 126                         dma-channel@0 {
 127                                 compatible = "fsl,mpc8544-dma-channel",
 128                                                 "fsl,eloplus-dma-channel";
 129                                 reg = <0x0 0x80>;
 130                                 cell-index = <0>;
 131                                 interrupt-parent = <&mpic>;
 132                                 interrupts = <20 2>;
 133                         };
 134                         dma-channel@80 {
 135                                 compatible = "fsl,mpc8544-dma-channel",
 136                                                 "fsl,eloplus-dma-channel";
 137                                 reg = <0x80 0x80>;
 138                                 cell-index = <1>;
 139                                 interrupt-parent = <&mpic>;
 140                                 interrupts = <21 2>;
 141                         };
 142                         dma-channel@100 {
 143                                 compatible = "fsl,mpc8544-dma-channel",
 144                                                 "fsl,eloplus-dma-channel";
 145                                 reg = <0x100 0x80>;
 146                                 cell-index = <2>;
 147                                 interrupt-parent = <&mpic>;
 148                                 interrupts = <22 2>;
 149                         };
 150                         dma-channel@180 {
 151                                 compatible = "fsl,mpc8544-dma-channel",
 152                                                 "fsl,eloplus-dma-channel";
 153                                 reg = <0x180 0x80>;
 154                                 cell-index = <3>;
 155                                 interrupt-parent = <&mpic>;
 156                                 interrupts = <23 2>;
 157                         };
 158                 };
 159
 160                 enet0: ethernet@24000 {
 161                         cell-index = <0>;
 162                         device_type = "network";
 163                         model = "TSEC";
 164                         compatible = "gianfar";
 165                         reg = <0x24000 0x1000>;
 166                         local-mac-address = [ 00 00 00 00 00 00 ];
 167                         interrupts = <29 2 30 2 34 2>;
 168                         interrupt-parent = <&mpic>;
 169                         phy-handle = <&phy0>;
 170                         phy-connection-type = "rgmii-id";
 171                 };
 172
 173                 enet1: ethernet@26000 {
 174                         cell-index = <1>;
 175                         device_type = "network";
 176                         model = "TSEC";
 177                         compatible = "gianfar";
 178                         reg = <0x26000 0x1000>;
 179                         local-mac-address = [ 00 00 00 00 00 00 ];
 180                         interrupts = <31 2 32 2 33 2>;
 181                         interrupt-parent = <&mpic>;
 182                         phy-handle = <&phy1>;
 183                         phy-connection-type = "rgmii-id";
 184                 };
 185
 186                 serial0: serial@4500 {
 187                         cell-index = <0>;
 188                         device_type = "serial";
 189                         compatible = "ns16550";
 190                         reg = <0x4500 0x100>;
 191                         clock-frequency = <0>;
 192                         interrupts = <42 2>;
 193                         interrupt-parent = <&mpic>;
 194                 };
 195
 196                 serial1: serial@4600 {
 197                         cell-index = <1>;
 198                         device_type = "serial";
 199                         compatible = "ns16550";
 200                         reg = <0x4600 0x100>;
 201                         clock-frequency = <0>;
 202                         interrupts = <42 2>;
 203                         interrupt-parent = <&mpic>;
 204                 };
 205
 206                 global-utilities@e0000 {        //global utilities block
 207                         compatible = "fsl,mpc8548-guts";
 208                         reg = <0xe0000 0x1000>;
 209                         fsl,has-rstcr;
 210                 };
 211
 212                 mpic: pic@40000 {
 213                         clock-frequency = <0>;
 214                         interrupt-controller;
 215                         #address-cells = <0>;
 216                         #interrupt-cells = <2>;
 217                         reg = <0x40000 0x40000>;
 218                         compatible = "chrp,open-pic";
 219                         device_type = "open-pic";
 220                         big-endian;
 221                 };
 222
 223                 msi@41600 {
 224                         compatible = "fsl,mpc8544-msi", "fsl,mpic-msi";
 225                         reg = <0x41600 0x80>;
 226                         msi-available-ranges = <0 0x100>;
 227                         interrupts = <
 228                                 0xe0 0
 229                                 0xe1 0
 230                                 0xe2 0
 231                                 0xe3 0
 232                                 0xe4 0
 233                                 0xe5 0
 234                                 0xe6 0
 235                                 0xe7 0>;
 236                         interrupt-parent = <&mpic>;
 237                 };
 238         };
 239
 240         pci0: pci@e0008000 {
 241                 cell-index = <0>;
 242                 compatible = "fsl,mpc8540-pci";
 243                 device_type = "pci";
 244                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 245                 interrupt-map = <
 246
 247                         /* IDSEL 0x11 J17 Slot 1 */
 248                         0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
 249                         0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
 250                         0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
 251                         0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
 252
 253                         /* IDSEL 0x12 J16 Slot 2 */
 254
 255                         0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
 256                         0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
 257                         0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
 258                         0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
 259
 260                 interrupt-parent = <&mpic>;
 261                 interrupts = <24 2>;
 262                 bus-range = <0 255>;
 263                 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
 264                           0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
 265                 clock-frequency = <66666666>;
 266                 #interrupt-cells = <1>;
 267                 #size-cells = <2>;
 268                 #address-cells = <3>;
 269                 reg = <0xe0008000 0x1000>;
 270         };
 271
 272         pci1: pcie@e0009000 {
 273                 cell-index = <1>;
 274                 compatible = "fsl,mpc8548-pcie";
 275                 device_type = "pci";
 276                 #interrupt-cells = <1>;
 277                 #size-cells = <2>;
 278                 #address-cells = <3>;
 279                 reg = <0xe0009000 0x1000>;
 280                 bus-range = <0 255>;
 281                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 282                           0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
 283                 clock-frequency = <33333333>;
 284                 interrupt-parent = <&mpic>;
 285                 interrupts = <26 2>;
 286                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 287                 interrupt-map = <
 288                         /* IDSEL 0x0 */
 289                         0000 0x0 0x0 0x1 &mpic 0x4 0x1
 290                         0000 0x0 0x0 0x2 &mpic 0x5 0x1
 291                         0000 0x0 0x0 0x3 &mpic 0x6 0x1
 292                         0000 0x0 0x0 0x4 &mpic 0x7 0x1
 293                         >;
 294                 pcie@0 {
 295                         reg = <0x0 0x0 0x0 0x0 0x0>;
 296                         #size-cells = <2>;
 297                         #address-cells = <3>;
 298                         device_type = "pci";
 299                         ranges = <0x2000000 0x0 0x80000000
 300                                   0x2000000 0x0 0x80000000
 301                                   0x0 0x20000000
 302
 303                                   0x1000000 0x0 0x0
 304                                   0x1000000 0x0 0x0
 305                                   0x0 0x10000>;
 306                 };
 307         };
 308
 309         pci2: pcie@e000a000 {
 310                 cell-index = <2>;
 311                 compatible = "fsl,mpc8548-pcie";
 312                 device_type = "pci";
 313                 #interrupt-cells = <1>;
 314                 #size-cells = <2>;
 315                 #address-cells = <3>;
 316                 reg = <0xe000a000 0x1000>;
 317                 bus-range = <0 255>;
 318                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 319                           0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
 320                 clock-frequency = <33333333>;
 321                 interrupt-parent = <&mpic>;
 322                 interrupts = <25 2>;
 323                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 324                 interrupt-map = <
 325                         /* IDSEL 0x0 */
 326                         0000 0x0 0x0 0x1 &mpic 0x0 0x1
 327                         0000 0x0 0x0 0x2 &mpic 0x1 0x1
 328                         0000 0x0 0x0 0x3 &mpic 0x2 0x1
 329                         0000 0x0 0x0 0x4 &mpic 0x3 0x1
 330                         >;
 331                 pcie@0 {
 332                         reg = <0x0 0x0 0x0 0x0 0x0>;
 333                         #size-cells = <2>;
 334                         #address-cells = <3>;
 335                         device_type = "pci";
 336                         ranges = <0x2000000 0x0 0xa0000000
 337                                   0x2000000 0x0 0xa0000000
 338                                   0x0 0x10000000
 339
 340                                   0x1000000 0x0 0x0
 341                                   0x1000000 0x0 0x0
 342                                   0x0 0x10000>;
 343                 };
 344         };
 345
 346         pci3: pcie@e000b000 {
 347                 cell-index = <3>;
 348                 compatible = "fsl,mpc8548-pcie";
 349                 device_type = "pci";
 350                 #interrupt-cells = <1>;
 351                 #size-cells = <2>;
 352                 #address-cells = <3>;
 353                 reg = <0xe000b000 0x1000>;
 354                 bus-range = <0 255>;
 355                 ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
 356                           0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
 357                 clock-frequency = <33333333>;
 358                 interrupt-parent = <&mpic>;
 359                 interrupts = <27 2>;
 360                 interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
 361                 interrupt-map = <
 362                         // IDSEL 0x1c  USB
 363                         0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
 364                         0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
 365                         0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
 366                         0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
 367
 368                         // IDSEL 0x1d  Audio
 369                         0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 370
 371                         // IDSEL 0x1e Legacy
 372                         0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
 373                         0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 374
 375                         // IDSEL 0x1f IDE/SATA
 376                         0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
 377                         0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
 378                 >;
 379
 380                 pcie@0 {
 381                         reg = <0x0 0x0 0x0 0x0 0x0>;
 382                         #size-cells = <2>;
 383                         #address-cells = <3>;
 384                         device_type = "pci";
 385                         ranges = <0x2000000 0x0 0xb0000000
 386                                   0x2000000 0x0 0xb0000000
 387                                   0x0 0x100000
 388
 389                                   0x1000000 0x0 0x0
 390                                   0x1000000 0x0 0x0
 391                                   0x0 0x100000>;
 392
 393                         uli1575@0 {
 394                                 reg = <0x0 0x0 0x0 0x0 0x0>;
 395                                 #size-cells = <2>;
 396                                 #address-cells = <3>;
 397                                 ranges = <0x2000000 0x0 0xb0000000
 398                                           0x2000000 0x0 0xb0000000
 399                                           0x0 0x100000
 400
 401                                           0x1000000 0x0 0x0
 402                                           0x1000000 0x0 0x0
 403                                           0x0 0x100000>;
 404                                 isa@1e {
 405                                         device_type = "isa";
 406                                         #interrupt-cells = <2>;
 407                                         #size-cells = <1>;
 408                                         #address-cells = <2>;
 409                                         reg = <0xf000 0x0 0x0 0x0 0x0>;
 410                                         ranges = <0x1 0x0
 411                                                   0x1000000 0x0 0x0
 412                                                   0x1000>;
 413                                         interrupt-parent = <&i8259>;
 414
 415                                         i8259: interrupt-controller@20 {
 416                                                 reg = <0x1 0x20 0x2
 417                                                        0x1 0xa0 0x2
 418                                                        0x1 0x4d0 0x2>;
 419                                                 interrupt-controller;
 420                                                 device_type = "interrupt-controller";
 421                                                 #address-cells = <0>;
 422                                                 #interrupt-cells = <2>;
 423                                                 compatible = "chrp,iic";
 424                                                 interrupts = <9 2>;
 425                                                 interrupt-parent = <&mpic>;
 426                                         };
 427
 428                                         i8042@60 {
 429                                                 #size-cells = <0>;
 430                                                 #address-cells = <1>;
 431                                                 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
 432                                                 interrupts = <1 3 12 3>;
 433                                                 interrupt-parent = <&i8259>;
 434
 435                                                 keyboard@0 {
 436                                                         reg = <0x0>;
 437                                                         compatible = "pnpPNP,303";
 438                                                 };
 439
 440                                                 mouse@1 {
 441                                                         reg = <0x1>;
 442                                                         compatible = "pnpPNP,f03";
 443                                                 };
 444                                         };
 445
 446                                         rtc@70 {
 447                                                 compatible = "pnpPNP,b00";
 448                                                 reg = <0x1 0x70 0x2>;
 449                                         };
 450
 451                                         gpio@400 {
 452                                                 reg = <0x1 0x400 0x80>;
 453                                         };
 454                                 };
 455                         };
 456                 };
 457         };
 458 };