arch/powerpc/boot/dts/mpc8541cds.dts

   1 /*
   2  * MPC8541 CDS Device Tree Source
   3  *
   4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8541CDS";
  16         compatible = "MPC8541CDS", "MPC85xxCDS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 serial0 = &serial0;
  24                 serial1 = &serial1;
  25                 pci0 = &pci0;
  26                 pci1 = &pci1;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 PowerPC,8541@0 {
  34                         device_type = "cpu";
  35                         reg = <0x0>;
  36                         d-cache-line-size = <32>;       // 32 bytes
  37                         i-cache-line-size = <32>;       // 32 bytes
  38                         d-cache-size = <0x8000>;                // L1, 32K
  39                         i-cache-size = <0x8000>;                // L1, 32K
  40                         timebase-frequency = <0>;       //  33 MHz, from uboot
  41                         bus-frequency = <0>;    // 166 MHz
  42                         clock-frequency = <0>;  // 825 MHz, from uboot
  43                 };
  44         };
  45
  46         memory {
  47                 device_type = "memory";
  48                 reg = <0x0 0x8000000>;  // 128M at 0x0
  49         };
  50
  51         soc8541@e0000000 {
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 device_type = "soc";
  55                 ranges = <0x0 0xe0000000 0x100000>;
  56                 reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
  57                 bus-frequency = <0>;
  58
  59                 memory-controller@2000 {
  60                         compatible = "fsl,8541-memory-controller";
  61                         reg = <0x2000 0x1000>;
  62                         interrupt-parent = <&mpic>;
  63                         interrupts = <18 2>;
  64                 };
  65
  66                 l2-cache-controller@20000 {
  67                         compatible = "fsl,8541-l2-cache-controller";
  68                         reg = <0x20000 0x1000>;
  69                         cache-line-size = <32>; // 32 bytes
  70                         cache-size = <0x40000>; // L2, 256K
  71                         interrupt-parent = <&mpic>;
  72                         interrupts = <16 2>;
  73                 };
  74
  75                 i2c@3000 {
  76                         #address-cells = <1>;
  77                         #size-cells = <0>;
  78                         cell-index = <0>;
  79                         compatible = "fsl-i2c";
  80                         reg = <0x3000 0x100>;
  81                         interrupts = <43 2>;
  82                         interrupt-parent = <&mpic>;
  83                         dfsrr;
  84                 };
  85
  86                 mdio@24520 {
  87                         #address-cells = <1>;
  88                         #size-cells = <0>;
  89                         compatible = "fsl,gianfar-mdio";
  90                         reg = <0x24520 0x20>;
  91
  92                         phy0: ethernet-phy@0 {
  93                                 interrupt-parent = <&mpic>;
  94                                 interrupts = <5 1>;
  95                                 reg = <0x0>;
  96                                 device_type = "ethernet-phy";
  97                         };
  98                         phy1: ethernet-phy@1 {
  99                                 interrupt-parent = <&mpic>;
 100                                 interrupts = <5 1>;
 101                                 reg = <0x1>;
 102                                 device_type = "ethernet-phy";
 103                         };
 104                 };
 105
 106                 enet0: ethernet@24000 {
 107                         cell-index = <0>;
 108                         device_type = "network";
 109                         model = "TSEC";
 110                         compatible = "gianfar";
 111                         reg = <0x24000 0x1000>;
 112                         local-mac-address = [ 00 00 00 00 00 00 ];
 113                         interrupts = <29 2 30 2 34 2>;
 114                         interrupt-parent = <&mpic>;
 115                         phy-handle = <&phy0>;
 116                 };
 117
 118                 enet1: ethernet@25000 {
 119                         cell-index = <1>;
 120                         device_type = "network";
 121                         model = "TSEC";
 122                         compatible = "gianfar";
 123                         reg = <0x25000 0x1000>;
 124                         local-mac-address = [ 00 00 00 00 00 00 ];
 125                         interrupts = <35 2 36 2 40 2>;
 126                         interrupt-parent = <&mpic>;
 127                         phy-handle = <&phy1>;
 128                 };
 129
 130                 serial0: serial@4500 {
 131                         cell-index = <0>;
 132                         device_type = "serial";
 133                         compatible = "ns16550";
 134                         reg = <0x4500 0x100>;   // reg base, size
 135                         clock-frequency = <0>;  // should we fill in in uboot?
 136                         interrupts = <42 2>;
 137                         interrupt-parent = <&mpic>;
 138                 };
 139
 140                 serial1: serial@4600 {
 141                         cell-index = <1>;
 142                         device_type = "serial";
 143                         compatible = "ns16550";
 144                         reg = <0x4600 0x100>;   // reg base, size
 145                         clock-frequency = <0>;  // should we fill in in uboot?
 146                         interrupts = <42 2>;
 147                         interrupt-parent = <&mpic>;
 148                 };
 149
 150                 mpic: pic@40000 {
 151                         interrupt-controller;
 152                         #address-cells = <0>;
 153                         #interrupt-cells = <2>;
 154                         reg = <0x40000 0x40000>;
 155                         compatible = "chrp,open-pic";
 156                         device_type = "open-pic";
 157                 };
 158
 159                 cpm@919c0 {
 160                         #address-cells = <1>;
 161                         #size-cells = <1>;
 162                         compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
 163                         reg = <0x919c0 0x30>;
 164                         ranges;
 165
 166                         muram@80000 {
 167                                 #address-cells = <1>;
 168                                 #size-cells = <1>;
 169                                 ranges = <0x0 0x80000 0x10000>;
 170
 171                                 data@0 {
 172                                         compatible = "fsl,cpm-muram-data";
 173                                         reg = <0x0 0x2000 0x9000 0x1000>;
 174                                 };
 175                         };
 176
 177                         brg@919f0 {
 178                                 compatible = "fsl,mpc8541-brg",
 179                                              "fsl,cpm2-brg",
 180                                              "fsl,cpm-brg";
 181                                 reg = <0x919f0 0x10 0x915f0 0x10>;
 182                         };
 183
 184                         cpmpic: pic@90c00 {
 185                                 interrupt-controller;
 186                                 #address-cells = <0>;
 187                                 #interrupt-cells = <2>;
 188                                 interrupts = <46 2>;
 189                                 interrupt-parent = <&mpic>;
 190                                 reg = <0x90c00 0x80>;
 191                                 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
 192                         };
 193                 };
 194         };
 195
 196         pci0: pci@e0008000 {
 197                 cell-index = <0>;
 198                 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
 199                 interrupt-map = <
 200
 201                         /* IDSEL 0x10 */
 202                         0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
 203                         0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
 204                         0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
 205                         0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
 206
 207                         /* IDSEL 0x11 */
 208                         0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
 209                         0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
 210                         0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
 211                         0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
 212
 213                         /* IDSEL 0x12 (Slot 1) */
 214                         0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
 215                         0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
 216                         0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
 217                         0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
 218
 219                         /* IDSEL 0x13 (Slot 2) */
 220                         0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
 221                         0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
 222                         0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
 223                         0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
 224
 225                         /* IDSEL 0x14 (Slot 3) */
 226                         0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
 227                         0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
 228                         0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
 229                         0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
 230
 231                         /* IDSEL 0x15 (Slot 4) */
 232                         0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
 233                         0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
 234                         0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
 235                         0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
 236
 237                         /* Bus 1 (Tundra Bridge) */
 238                         /* IDSEL 0x12 (ISA bridge) */
 239                         0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
 240                         0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
 241                         0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
 242                         0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 243                 interrupt-parent = <&mpic>;
 244                 interrupts = <24 2>;
 245                 bus-range = <0 0>;
 246                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 247                           0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
 248                 clock-frequency = <66666666>;
 249                 #interrupt-cells = <1>;
 250                 #size-cells = <2>;
 251                 #address-cells = <3>;
 252                 reg = <0xe0008000 0x1000>;
 253                 compatible = "fsl,mpc8540-pci";
 254                 device_type = "pci";
 255
 256                 i8259@19000 {
 257                         interrupt-controller;
 258                         device_type = "interrupt-controller";
 259                         reg = <0x19000 0x0 0x0 0x0 0x1>;
 260                         #address-cells = <0>;
 261                         #interrupt-cells = <2>;
 262                         compatible = "chrp,iic";
 263                         interrupts = <1>;
 264                         interrupt-parent = <&pci0>;
 265                 };
 266         };
 267
 268         pci1: pci@e0009000 {
 269                 cell-index = <1>;
 270                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 271                 interrupt-map = <
 272
 273                         /* IDSEL 0x15 */
 274                         0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
 275                         0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
 276                         0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
 277                         0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
 278                 interrupt-parent = <&mpic>;
 279                 interrupts = <25 2>;
 280                 bus-range = <0 0>;
 281                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
 282                           0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
 283                 clock-frequency = <66666666>;
 284                 #interrupt-cells = <1>;
 285                 #size-cells = <2>;
 286                 #address-cells = <3>;
 287                 reg = <0xe0009000 0x1000>;
 288                 compatible = "fsl,mpc8540-pci";
 289                 device_type = "pci";
 290         };
 291 };