arch/powerpc/boot/dts/mpc8378_rdb.dts

   1 /*
   2  * MPC8378E RDB Device Tree Source
   3  *
   4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         compatible = "fsl,mpc8378rdb";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 ethernet0 = &enet0;
  21                 ethernet1 = &enet1;
  22                 serial0 = &serial0;
  23                 serial1 = &serial1;
  24                 pci0 = &pci0;
  25                 pci1 = &pci1;
  26                 pci2 = &pci2;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 PowerPC,8378@0 {
  34                         device_type = "cpu";
  35                         reg = <0x0>;
  36                         d-cache-line-size = <32>;
  37                         i-cache-line-size = <32>;
  38                         d-cache-size = <32768>;
  39                         i-cache-size = <32768>;
  40                         timebase-frequency = <0>;
  41                         bus-frequency = <0>;
  42                         clock-frequency = <0>;
  43                 };
  44         };
  45
  46         memory {
  47                 device_type = "memory";
  48                 reg = <0x00000000 0x10000000>;  // 256MB at 0
  49         };
  50
  51         localbus@e0005000 {
  52                 #address-cells = <2>;
  53                 #size-cells = <1>;
  54                 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
  55                 reg = <0xe0005000 0x1000>;
  56                 interrupts = <77 0x8>;
  57                 interrupt-parent = <&ipic>;
  58
  59                 // CS0 and CS1 are swapped when
  60                 // booting from nand, but the
  61                 // addresses are the same.
  62                 ranges = <0x0 0x0 0xfe000000 0x00800000
  63                           0x1 0x0 0xe0600000 0x00008000
  64                           0x2 0x0 0xf0000000 0x00020000
  65                           0x3 0x0 0xfa000000 0x00008000>;
  66
  67                 flash@0,0 {
  68                         #address-cells = <1>;
  69                         #size-cells = <1>;
  70                         compatible = "cfi-flash";
  71                         reg = <0x0 0x0 0x800000>;
  72                         bank-width = <2>;
  73                         device-width = <1>;
  74                 };
  75
  76                 nand@1,0 {
  77                         #address-cells = <1>;
  78                         #size-cells = <1>;
  79                         compatible = "fsl,mpc8378-fcm-nand",
  80                                      "fsl,elbc-fcm-nand";
  81                         reg = <0x1 0x0 0x8000>;
  82
  83                         u-boot@0 {
  84                                 reg = <0x0 0x100000>;
  85                                 read-only;
  86                         };
  87
  88                         kernel@100000 {
  89                                 reg = <0x100000 0x300000>;
  90                         };
  91                         fs@400000 {
  92                                 reg = <0x400000 0x1c00000>;
  93                         };
  94                 };
  95         };
  96
  97         immr@e0000000 {
  98                 #address-cells = <1>;
  99                 #size-cells = <1>;
 100                 device_type = "soc";
 101                 compatible = "simple-bus";
 102                 ranges = <0x0 0xe0000000 0x00100000>;
 103                 reg = <0xe0000000 0x00000200>;
 104                 bus-frequency = <0>;
 105
 106                 wdt@200 {
 107                         device_type = "watchdog";
 108                         compatible = "mpc83xx_wdt";
 109                         reg = <0x200 0x100>;
 110                 };
 111
 112                 gpio1: gpio-controller@c00 {
 113                         #gpio-cells = <2>;
 114                         compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
 115                         reg = <0xc00 0x100>;
 116                         interrupts = <74 0x8>;
 117                         interrupt-parent = <&ipic>;
 118                         gpio-controller;
 119                 };
 120
 121                 gpio2: gpio-controller@d00 {
 122                         #gpio-cells = <2>;
 123                         compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
 124                         reg = <0xd00 0x100>;
 125                         interrupts = <75 0x8>;
 126                         interrupt-parent = <&ipic>;
 127                         gpio-controller;
 128                 };
 129
 130                 sleep-nexus {
 131                         #address-cells = <1>;
 132                         #size-cells = <1>;
 133                         compatible = "simple-bus";
 134                         sleep = <&pmc 0x0c000000>;
 135                         ranges;
 136
 137                         i2c@3000 {
 138                                 #address-cells = <1>;
 139                                 #size-cells = <0>;
 140                                 cell-index = <0>;
 141                                 compatible = "fsl-i2c";
 142                                 reg = <0x3000 0x100>;
 143                                 interrupts = <14 0x8>;
 144                                 interrupt-parent = <&ipic>;
 145                                 dfsrr;
 146
 147                                 dtt@48 {
 148                                         compatible = "national,lm75";
 149                                         reg = <0x48>;
 150                                 };
 151
 152                                 at24@50 {
 153                                         compatible = "at24,24c256";
 154                                         reg = <0x50>;
 155                                 };
 156
 157                                 rtc@68 {
 158                                         compatible = "dallas,ds1339";
 159                                         reg = <0x68>;
 160                                 };
 161
 162                                 mcu_pio: mcu@a {
 163                                         #gpio-cells = <2>;
 164                                         compatible = "fsl,mc9s08qg8-mpc8378erdb",
 165                                                      "fsl,mcu-mpc8349emitx";
 166                                         reg = <0x0a>;
 167                                         gpio-controller;
 168                                 };
 169                         };
 170
 171                         sdhci@2e000 {
 172                                 compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
 173                                 reg = <0x2e000 0x1000>;
 174                                 interrupts = <42 0x8>;
 175                                 interrupt-parent = <&ipic>;
 176                                 /* Filled in by U-Boot */
 177                                 clock-frequency = <0>;
 178                         };
 179                 };
 180
 181                 i2c@3100 {
 182                         #address-cells = <1>;
 183                         #size-cells = <0>;
 184                         cell-index = <1>;
 185                         compatible = "fsl-i2c";
 186                         reg = <0x3100 0x100>;
 187                         interrupts = <15 0x8>;
 188                         interrupt-parent = <&ipic>;
 189                         dfsrr;
 190                 };
 191
 192                 spi@7000 {
 193                         cell-index = <0>;
 194                         compatible = "fsl,spi";
 195                         reg = <0x7000 0x1000>;
 196                         interrupts = <16 0x8>;
 197                         interrupt-parent = <&ipic>;
 198                         mode = "cpu";
 199                 };
 200
 201                 dma@82a8 {
 202                         #address-cells = <1>;
 203                         #size-cells = <1>;
 204                         compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
 205                         reg = <0x82a8 4>;
 206                         ranges = <0 0x8100 0x1a8>;
 207                         interrupt-parent = <&ipic>;
 208                         interrupts = <71 8>;
 209                         cell-index = <0>;
 210                         dma-channel@0 {
 211                                 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
 212                                 reg = <0 0x80>;
 213                                 cell-index = <0>;
 214                                 interrupt-parent = <&ipic>;
 215                                 interrupts = <71 8>;
 216                         };
 217                         dma-channel@80 {
 218                                 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
 219                                 reg = <0x80 0x80>;
 220                                 cell-index = <1>;
 221                                 interrupt-parent = <&ipic>;
 222                                 interrupts = <71 8>;
 223                         };
 224                         dma-channel@100 {
 225                                 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
 226                                 reg = <0x100 0x80>;
 227                                 cell-index = <2>;
 228                                 interrupt-parent = <&ipic>;
 229                                 interrupts = <71 8>;
 230                         };
 231                         dma-channel@180 {
 232                                 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
 233                                 reg = <0x180 0x28>;
 234                                 cell-index = <3>;
 235                                 interrupt-parent = <&ipic>;
 236                                 interrupts = <71 8>;
 237                         };
 238                 };
 239
 240                 usb@23000 {
 241                         compatible = "fsl-usb2-dr";
 242                         reg = <0x23000 0x1000>;
 243                         #address-cells = <1>;
 244                         #size-cells = <0>;
 245                         interrupt-parent = <&ipic>;
 246                         interrupts = <38 0x8>;
 247                         phy_type = "ulpi";
 248                         sleep = <&pmc 0x00c00000>;
 249                 };
 250
 251                 mdio@24520 {
 252                         #address-cells = <1>;
 253                         #size-cells = <0>;
 254                         compatible = "fsl,gianfar-mdio";
 255                         reg = <0x24520 0x20>;
 256                         phy2: ethernet-phy@2 {
 257                                 interrupt-parent = <&ipic>;
 258                                 interrupts = <17 0x8>;
 259                                 reg = <0x2>;
 260                                 device_type = "ethernet-phy";
 261                         };
 262                         tbi0: tbi-phy@11 {
 263                                 reg = <0x11>;
 264                                 device_type = "tbi-phy";
 265                         };
 266                 };
 267
 268                 mdio@25520 {
 269                         #address-cells = <1>;
 270                         #size-cells = <0>;
 271                         compatible = "fsl,gianfar-tbi";
 272                         reg = <0x25520 0x20>;
 273
 274                         tbi1: tbi-phy@11 {
 275                                 reg = <0x11>;
 276                                 device_type = "tbi-phy";
 277                         };
 278                 };
 279
 280
 281                 enet0: ethernet@24000 {
 282                         cell-index = <0>;
 283                         device_type = "network";
 284                         model = "eTSEC";
 285                         compatible = "gianfar";
 286                         reg = <0x24000 0x1000>;
 287                         local-mac-address = [ 00 00 00 00 00 00 ];
 288                         interrupts = <32 0x8 33 0x8 34 0x8>;
 289                         phy-connection-type = "mii";
 290                         interrupt-parent = <&ipic>;
 291                         phy-handle = <&phy2>;
 292                         sleep = <&pmc 0xc0000000>;
 293                         fsl,magic-packet;
 294                 };
 295
 296                 enet1: ethernet@25000 {
 297                         cell-index = <1>;
 298                         device_type = "network";
 299                         model = "eTSEC";
 300                         compatible = "gianfar";
 301                         reg = <0x25000 0x1000>;
 302                         local-mac-address = [ 00 00 00 00 00 00 ];
 303                         interrupts = <35 0x8 36 0x8 37 0x8>;
 304                         phy-connection-type = "mii";
 305                         interrupt-parent = <&ipic>;
 306                         fixed-link = <1 1 1000 0 0>;
 307                         sleep = <&pmc 0x30000000>;
 308                         fsl,magic-packet;
 309                 };
 310
 311                 serial0: serial@4500 {
 312                         cell-index = <0>;
 313                         device_type = "serial";
 314                         compatible = "ns16550";
 315                         reg = <0x4500 0x100>;
 316                         clock-frequency = <0>;
 317                         interrupts = <9 0x8>;
 318                         interrupt-parent = <&ipic>;
 319                 };
 320
 321                 serial1: serial@4600 {
 322                         cell-index = <1>;
 323                         device_type = "serial";
 324                         compatible = "ns16550";
 325                         reg = <0x4600 0x100>;
 326                         clock-frequency = <0>;
 327                         interrupts = <10 0x8>;
 328                         interrupt-parent = <&ipic>;
 329                 };
 330
 331                 crypto@30000 {
 332                         compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
 333                                      "fsl,sec2.1", "fsl,sec2.0";
 334                         reg = <0x30000 0x10000>;
 335                         interrupts = <11 0x8>;
 336                         interrupt-parent = <&ipic>;
 337                         fsl,num-channels = <4>;
 338                         fsl,channel-fifo-len = <24>;
 339                         fsl,exec-units-mask = <0x9fe>;
 340                         fsl,descriptor-types-mask = <0x3ab0ebf>;
 341                         sleep = <&pmc 0x03000000>;
 342                 };
 343
 344                 /* IPIC
 345                  * interrupts cell = <intr #, sense>
 346                  * sense values match linux IORESOURCE_IRQ_* defines:
 347                  * sense == 8: Level, low assertion
 348                  * sense == 2: Edge, high-to-low change
 349                  */
 350                 ipic: interrupt-controller@700 {
 351                         compatible = "fsl,ipic";
 352                         interrupt-controller;
 353                         #address-cells = <0>;
 354                         #interrupt-cells = <2>;
 355                         reg = <0x700 0x100>;
 356                 };
 357
 358                 pmc: power@b00 {
 359                         compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc";
 360                         reg = <0xb00 0x100 0xa00 0x100>;
 361                         interrupts = <80 0x8>;
 362                         interrupt-parent = <&ipic>;
 363                 };
 364         };
 365
 366         pci0: pci@e0008500 {
 367                 interrupt-map-mask = <0xf800 0 0 7>;
 368                 interrupt-map = <
 369                                 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
 370
 371                                 /* IDSEL AD14 IRQ6 inta */
 372                                  0x7000 0x0 0x0 0x1 &ipic 22 0x8
 373
 374                                 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
 375                                  0x7800 0x0 0x0 0x1 &ipic 21 0x8
 376                                  0x7800 0x0 0x0 0x2 &ipic 22 0x8
 377                                  0x7800 0x0 0x0 0x4 &ipic 23 0x8
 378
 379                                 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
 380                                  0xE000 0x0 0x0 0x1 &ipic 23 0x8
 381                                  0xE000 0x0 0x0 0x2 &ipic 21 0x8
 382                                  0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
 383                 interrupt-parent = <&ipic>;
 384                 interrupts = <66 0x8>;
 385                 bus-range = <0 0>;
 386                 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 387                           0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 388                           0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
 389                 sleep = <&pmc 0x00010000>;
 390                 clock-frequency = <66666666>;
 391                 #interrupt-cells = <1>;
 392                 #size-cells = <2>;
 393                 #address-cells = <3>;
 394                 reg = <0xe0008500 0x100         /* internal registers */
 395                        0xe0008300 0x8>;         /* config space access registers */
 396                 compatible = "fsl,mpc8349-pci";
 397                 device_type = "pci";
 398         };
 399
 400         pci1: pcie@e0009000 {
 401                 #address-cells = <3>;
 402                 #size-cells = <2>;
 403                 #interrupt-cells = <1>;
 404                 device_type = "pci";
 405                 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
 406                 reg = <0xe0009000 0x00001000>;
 407                 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
 408                           0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
 409                 bus-range = <0 255>;
 410                 interrupt-map-mask = <0xf800 0 0 7>;
 411                 interrupt-map = <0 0 0 1 &ipic 1 8
 412                                  0 0 0 2 &ipic 1 8
 413                                  0 0 0 3 &ipic 1 8
 414                                  0 0 0 4 &ipic 1 8>;
 415                 sleep = <&pmc 0x00300000>;
 416                 clock-frequency = <0>;
 417
 418                 pcie@0 {
 419                         #address-cells = <3>;
 420                         #size-cells = <2>;
 421                         device_type = "pci";
 422                         reg = <0 0 0 0 0>;
 423                         ranges = <0x02000000 0 0xa8000000
 424                                   0x02000000 0 0xa8000000
 425                                   0 0x10000000
 426                                   0x01000000 0 0x00000000
 427                                   0x01000000 0 0x00000000
 428                                   0 0x00800000>;
 429                 };
 430         };
 431
 432         pci2: pcie@e000a000 {
 433                 #address-cells = <3>;
 434                 #size-cells = <2>;
 435                 #interrupt-cells = <1>;
 436                 device_type = "pci";
 437                 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
 438                 reg = <0xe000a000 0x00001000>;
 439                 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
 440                           0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
 441                 bus-range = <0 255>;
 442                 interrupt-map-mask = <0xf800 0 0 7>;
 443                 interrupt-map = <0 0 0 1 &ipic 2 8
 444                                  0 0 0 2 &ipic 2 8
 445                                  0 0 0 3 &ipic 2 8
 446                                  0 0 0 4 &ipic 2 8>;
 447                 sleep = <&pmc 0x000c0000>;
 448                 clock-frequency = <0>;
 449
 450                 pcie@0 {
 451                         #address-cells = <3>;
 452                         #size-cells = <2>;
 453                         device_type = "pci";
 454                         reg = <0 0 0 0 0>;
 455                         ranges = <0x02000000 0 0xc8000000
 456                                   0x02000000 0 0xc8000000
 457                                   0 0x10000000
 458                                   0x01000000 0 0x00000000
 459                                   0x01000000 0 0x00000000
 460                                   0 0x00800000>;
 461                 };
 462         };
 463 };