2 * MPC8378E RDB Device Tree Source
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 compatible = "fsl,mpc8378rdb";
36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <32768>;
39 i-cache-size = <32768>;
40 timebase-frequency = <0>;
42 clock-frequency = <0>;
47 device_type = "memory";
48 reg = <0x00000000 0x10000000>; // 256MB at 0
54 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
55 reg = <0xe0005000 0x1000>;
56 interrupts = <77 0x8>;
57 interrupt-parent = <&ipic>;
59 // CS0 and CS1 are swapped when
60 // booting from nand, but the
61 // addresses are the same.
62 ranges = <0x0 0x0 0xfe000000 0x00800000
63 0x1 0x0 0xe0600000 0x00008000
64 0x2 0x0 0xf0000000 0x00020000
65 0x3 0x0 0xfa000000 0x00008000>;
70 compatible = "cfi-flash";
71 reg = <0x0 0x0 0x800000>;
79 compatible = "fsl,mpc8378-fcm-nand",
81 reg = <0x1 0x0 0x8000>;
89 reg = <0x100000 0x300000>;
92 reg = <0x400000 0x1c00000>;
101 compatible = "simple-bus";
102 ranges = <0x0 0xe0000000 0x00100000>;
103 reg = <0xe0000000 0x00000200>;
107 device_type = "watchdog";
108 compatible = "mpc83xx_wdt";
112 gpio1: gpio-controller@c00 {
114 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
116 interrupts = <74 0x8>;
117 interrupt-parent = <&ipic>;
121 gpio2: gpio-controller@d00 {
123 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
125 interrupts = <75 0x8>;
126 interrupt-parent = <&ipic>;
131 #address-cells = <1>;
133 compatible = "simple-bus";
134 sleep = <&pmc 0x0c000000>;
138 #address-cells = <1>;
141 compatible = "fsl-i2c";
142 reg = <0x3000 0x100>;
143 interrupts = <14 0x8>;
144 interrupt-parent = <&ipic>;
148 compatible = "national,lm75";
153 compatible = "at24,24c256";
158 compatible = "dallas,ds1339";
164 compatible = "fsl,mc9s08qg8-mpc8378erdb",
165 "fsl,mcu-mpc8349emitx";
172 compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
173 reg = <0x2e000 0x1000>;
174 interrupts = <42 0x8>;
175 interrupt-parent = <&ipic>;
176 /* Filled in by U-Boot */
177 clock-frequency = <0>;
182 #address-cells = <1>;
185 compatible = "fsl-i2c";
186 reg = <0x3100 0x100>;
187 interrupts = <15 0x8>;
188 interrupt-parent = <&ipic>;
194 compatible = "fsl,spi";
195 reg = <0x7000 0x1000>;
196 interrupts = <16 0x8>;
197 interrupt-parent = <&ipic>;
202 #address-cells = <1>;
204 compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
206 ranges = <0 0x8100 0x1a8>;
207 interrupt-parent = <&ipic>;
211 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
214 interrupt-parent = <&ipic>;
218 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
221 interrupt-parent = <&ipic>;
225 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
228 interrupt-parent = <&ipic>;
232 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
235 interrupt-parent = <&ipic>;
241 compatible = "fsl-usb2-dr";
242 reg = <0x23000 0x1000>;
243 #address-cells = <1>;
245 interrupt-parent = <&ipic>;
246 interrupts = <38 0x8>;
248 sleep = <&pmc 0x00c00000>;
252 #address-cells = <1>;
254 compatible = "fsl,gianfar-mdio";
255 reg = <0x24520 0x20>;
256 phy2: ethernet-phy@2 {
257 interrupt-parent = <&ipic>;
258 interrupts = <17 0x8>;
260 device_type = "ethernet-phy";
264 device_type = "tbi-phy";
269 #address-cells = <1>;
271 compatible = "fsl,gianfar-tbi";
272 reg = <0x25520 0x20>;
276 device_type = "tbi-phy";
281 enet0: ethernet@24000 {
283 device_type = "network";
285 compatible = "gianfar";
286 reg = <0x24000 0x1000>;
287 local-mac-address = [ 00 00 00 00 00 00 ];
288 interrupts = <32 0x8 33 0x8 34 0x8>;
289 phy-connection-type = "mii";
290 interrupt-parent = <&ipic>;
291 phy-handle = <&phy2>;
292 sleep = <&pmc 0xc0000000>;
296 enet1: ethernet@25000 {
298 device_type = "network";
300 compatible = "gianfar";
301 reg = <0x25000 0x1000>;
302 local-mac-address = [ 00 00 00 00 00 00 ];
303 interrupts = <35 0x8 36 0x8 37 0x8>;
304 phy-connection-type = "mii";
305 interrupt-parent = <&ipic>;
306 fixed-link = <1 1 1000 0 0>;
307 sleep = <&pmc 0x30000000>;
311 serial0: serial@4500 {
313 device_type = "serial";
314 compatible = "ns16550";
315 reg = <0x4500 0x100>;
316 clock-frequency = <0>;
317 interrupts = <9 0x8>;
318 interrupt-parent = <&ipic>;
321 serial1: serial@4600 {
323 device_type = "serial";
324 compatible = "ns16550";
325 reg = <0x4600 0x100>;
326 clock-frequency = <0>;
327 interrupts = <10 0x8>;
328 interrupt-parent = <&ipic>;
332 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
333 "fsl,sec2.1", "fsl,sec2.0";
334 reg = <0x30000 0x10000>;
335 interrupts = <11 0x8>;
336 interrupt-parent = <&ipic>;
337 fsl,num-channels = <4>;
338 fsl,channel-fifo-len = <24>;
339 fsl,exec-units-mask = <0x9fe>;
340 fsl,descriptor-types-mask = <0x3ab0ebf>;
341 sleep = <&pmc 0x03000000>;
345 * interrupts cell = <intr #, sense>
346 * sense values match linux IORESOURCE_IRQ_* defines:
347 * sense == 8: Level, low assertion
348 * sense == 2: Edge, high-to-low change
350 ipic: interrupt-controller@700 {
351 compatible = "fsl,ipic";
352 interrupt-controller;
353 #address-cells = <0>;
354 #interrupt-cells = <2>;
359 compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc";
360 reg = <0xb00 0x100 0xa00 0x100>;
361 interrupts = <80 0x8>;
362 interrupt-parent = <&ipic>;
367 interrupt-map-mask = <0xf800 0 0 7>;
369 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
371 /* IDSEL AD14 IRQ6 inta */
372 0x7000 0x0 0x0 0x1 &ipic 22 0x8
374 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
375 0x7800 0x0 0x0 0x1 &ipic 21 0x8
376 0x7800 0x0 0x0 0x2 &ipic 22 0x8
377 0x7800 0x0 0x0 0x4 &ipic 23 0x8
379 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
380 0xE000 0x0 0x0 0x1 &ipic 23 0x8
381 0xE000 0x0 0x0 0x2 &ipic 21 0x8
382 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
383 interrupt-parent = <&ipic>;
384 interrupts = <66 0x8>;
386 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
387 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
388 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
389 sleep = <&pmc 0x00010000>;
390 clock-frequency = <66666666>;
391 #interrupt-cells = <1>;
393 #address-cells = <3>;
394 reg = <0xe0008500 0x100 /* internal registers */
395 0xe0008300 0x8>; /* config space access registers */
396 compatible = "fsl,mpc8349-pci";
400 pci1: pcie@e0009000 {
401 #address-cells = <3>;
403 #interrupt-cells = <1>;
405 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
406 reg = <0xe0009000 0x00001000>;
407 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
408 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
410 interrupt-map-mask = <0xf800 0 0 7>;
411 interrupt-map = <0 0 0 1 &ipic 1 8
415 sleep = <&pmc 0x00300000>;
416 clock-frequency = <0>;
419 #address-cells = <3>;
423 ranges = <0x02000000 0 0xa8000000
424 0x02000000 0 0xa8000000
426 0x01000000 0 0x00000000
427 0x01000000 0 0x00000000
432 pci2: pcie@e000a000 {
433 #address-cells = <3>;
435 #interrupt-cells = <1>;
437 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
438 reg = <0xe000a000 0x00001000>;
439 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
440 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
442 interrupt-map-mask = <0xf800 0 0 7>;
443 interrupt-map = <0 0 0 1 &ipic 2 8
447 sleep = <&pmc 0x000c0000>;
448 clock-frequency = <0>;
451 #address-cells = <3>;
455 ranges = <0x02000000 0 0xc8000000
456 0x02000000 0 0xc8000000
458 0x01000000 0 0x00000000
459 0x01000000 0 0x00000000