2 * MPC8378E MDS Device Tree Source
4 * Copyright 2007 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 model = "fsl,mpc8378emds";
16 compatible = "fsl,mpc8378emds","fsl,mpc837xmds";
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
40 i-cache-size = <32768>;
41 timebase-frequency = <0>;
43 clock-frequency = <0>;
48 device_type = "memory";
49 reg = <0x00000000 0x20000000>; // 512MB at 0
55 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
56 reg = <0xe0005000 0x1000>;
57 interrupts = <77 0x8>;
58 interrupt-parent = <&ipic>;
60 // booting from NOR flash
61 ranges = <0 0x0 0xfe000000 0x02000000
62 1 0x0 0xf8000000 0x00008000
63 3 0x0 0xe0600000 0x00008000>;
68 compatible = "cfi-flash";
69 reg = <0 0x0 0x2000000>;
79 reg = <0x100000 0x800000>;
83 reg = <0x1d00000 0x200000>;
87 reg = <0x1f00000 0x100000>;
93 compatible = "fsl,mpc837xmds-bcsr";
99 compatible = "fsl,mpc8378-fcm-nand",
101 reg = <3 0x0 0x8000>;
104 reg = <0x0 0x100000>;
109 reg = <0x100000 0x300000>;
113 reg = <0x400000 0x1c00000>;
119 #address-cells = <1>;
122 compatible = "simple-bus";
123 ranges = <0x0 0xe0000000 0x00100000>;
124 reg = <0xe0000000 0x00000200>;
128 compatible = "mpc83xx_wdt";
133 #address-cells = <1>;
136 compatible = "fsl-i2c";
137 reg = <0x3000 0x100>;
138 interrupts = <14 0x8>;
139 interrupt-parent = <&ipic>;
143 compatible = "dallas,ds1374";
145 interrupts = <19 0x8>;
146 interrupt-parent = <&ipic>;
151 #address-cells = <1>;
154 compatible = "fsl-i2c";
155 reg = <0x3100 0x100>;
156 interrupts = <15 0x8>;
157 interrupt-parent = <&ipic>;
163 compatible = "fsl,spi";
164 reg = <0x7000 0x1000>;
165 interrupts = <16 0x8>;
166 interrupt-parent = <&ipic>;
171 #address-cells = <1>;
173 compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
175 ranges = <0 0x8100 0x1a8>;
176 interrupt-parent = <&ipic>;
180 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
183 interrupt-parent = <&ipic>;
187 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
190 interrupt-parent = <&ipic>;
194 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
197 interrupt-parent = <&ipic>;
201 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
204 interrupt-parent = <&ipic>;
210 compatible = "fsl-usb2-dr";
211 reg = <0x23000 0x1000>;
212 #address-cells = <1>;
214 interrupt-parent = <&ipic>;
215 interrupts = <38 0x8>;
221 #address-cells = <1>;
223 compatible = "fsl,gianfar-mdio";
224 reg = <0x24520 0x20>;
225 phy2: ethernet-phy@2 {
226 interrupt-parent = <&ipic>;
227 interrupts = <17 0x8>;
229 device_type = "ethernet-phy";
231 phy3: ethernet-phy@3 {
232 interrupt-parent = <&ipic>;
233 interrupts = <18 0x8>;
235 device_type = "ethernet-phy";
239 device_type = "tbi-phy";
244 #address-cells = <1>;
246 compatible = "fsl,gianfar-tbi";
247 reg = <0x25520 0x20>;
251 device_type = "tbi-phy";
256 enet0: ethernet@24000 {
258 device_type = "network";
260 compatible = "gianfar";
261 reg = <0x24000 0x1000>;
262 local-mac-address = [ 00 00 00 00 00 00 ];
263 interrupts = <32 0x8 33 0x8 34 0x8>;
264 phy-connection-type = "mii";
265 interrupt-parent = <&ipic>;
266 tbi-handle = <&tbi0>;
267 phy-handle = <&phy2>;
270 enet1: ethernet@25000 {
272 device_type = "network";
274 compatible = "gianfar";
275 reg = <0x25000 0x1000>;
276 local-mac-address = [ 00 00 00 00 00 00 ];
277 interrupts = <35 0x8 36 0x8 37 0x8>;
278 phy-connection-type = "mii";
279 interrupt-parent = <&ipic>;
280 tbi-handle = <&tbi1>;
281 phy-handle = <&phy3>;
284 serial0: serial@4500 {
286 device_type = "serial";
287 compatible = "ns16550";
288 reg = <0x4500 0x100>;
289 clock-frequency = <0>;
290 interrupts = <9 0x8>;
291 interrupt-parent = <&ipic>;
294 serial1: serial@4600 {
296 device_type = "serial";
297 compatible = "ns16550";
298 reg = <0x4600 0x100>;
299 clock-frequency = <0>;
300 interrupts = <10 0x8>;
301 interrupt-parent = <&ipic>;
305 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
306 "fsl,sec2.1", "fsl,sec2.0";
307 reg = <0x30000 0x10000>;
308 interrupts = <11 0x8>;
309 interrupt-parent = <&ipic>;
310 fsl,num-channels = <4>;
311 fsl,channel-fifo-len = <24>;
312 fsl,exec-units-mask = <0x9fe>;
313 fsl,descriptor-types-mask = <0x3ab0ebf>;
318 compatible = "fsl,esdhc";
319 reg = <0x2e000 0x1000>;
320 interrupts = <42 0x8>;
321 interrupt-parent = <&ipic>;
325 * interrupts cell = <intr #, sense>
326 * sense values match linux IORESOURCE_IRQ_* defines:
327 * sense == 8: Level, low assertion
328 * sense == 2: Edge, high-to-low change
331 compatible = "fsl,ipic";
332 interrupt-controller;
333 #address-cells = <0>;
334 #interrupt-cells = <2>;
341 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
345 0x8800 0x0 0x0 0x1 &ipic 20 0x8
346 0x8800 0x0 0x0 0x2 &ipic 21 0x8
347 0x8800 0x0 0x0 0x3 &ipic 22 0x8
348 0x8800 0x0 0x0 0x4 &ipic 23 0x8
351 0x9000 0x0 0x0 0x1 &ipic 22 0x8
352 0x9000 0x0 0x0 0x2 &ipic 23 0x8
353 0x9000 0x0 0x0 0x3 &ipic 20 0x8
354 0x9000 0x0 0x0 0x4 &ipic 21 0x8
357 0x9800 0x0 0x0 0x1 &ipic 23 0x8
358 0x9800 0x0 0x0 0x2 &ipic 20 0x8
359 0x9800 0x0 0x0 0x3 &ipic 21 0x8
360 0x9800 0x0 0x0 0x4 &ipic 22 0x8
363 0xa800 0x0 0x0 0x1 &ipic 20 0x8
364 0xa800 0x0 0x0 0x2 &ipic 21 0x8
365 0xa800 0x0 0x0 0x3 &ipic 22 0x8
366 0xa800 0x0 0x0 0x4 &ipic 23 0x8
369 0xb000 0x0 0x0 0x1 &ipic 23 0x8
370 0xb000 0x0 0x0 0x2 &ipic 20 0x8
371 0xb000 0x0 0x0 0x3 &ipic 21 0x8
372 0xb000 0x0 0x0 0x4 &ipic 22 0x8
375 0xb800 0x0 0x0 0x1 &ipic 22 0x8
376 0xb800 0x0 0x0 0x2 &ipic 23 0x8
377 0xb800 0x0 0x0 0x3 &ipic 20 0x8
378 0xb800 0x0 0x0 0x4 &ipic 21 0x8
381 0xc000 0x0 0x0 0x1 &ipic 21 0x8
382 0xc000 0x0 0x0 0x2 &ipic 22 0x8
383 0xc000 0x0 0x0 0x3 &ipic 23 0x8
384 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
385 interrupt-parent = <&ipic>;
386 interrupts = <66 0x8>;
387 bus-range = <0x0 0x0>;
388 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
389 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
390 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
391 clock-frequency = <0>;
392 #interrupt-cells = <1>;
394 #address-cells = <3>;
395 reg = <0xe0008500 0x100 /* internal registers */
396 0xe0008300 0x8>; /* config space access registers */
397 compatible = "fsl,mpc8349-pci";
401 pci1: pcie@e0009000 {
402 #address-cells = <3>;
404 #interrupt-cells = <1>;
406 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
407 reg = <0xe0009000 0x00001000>;
408 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
409 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
411 interrupt-map-mask = <0xf800 0 0 7>;
412 interrupt-map = <0 0 0 1 &ipic 1 8
416 clock-frequency = <0>;
419 #address-cells = <3>;
423 ranges = <0x02000000 0 0xa8000000
424 0x02000000 0 0xa8000000
426 0x01000000 0 0x00000000
427 0x01000000 0 0x00000000
432 pci2: pcie@e000a000 {
433 #address-cells = <3>;
435 #interrupt-cells = <1>;
437 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
438 reg = <0xe000a000 0x00001000>;
439 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
440 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
442 interrupt-map-mask = <0xf800 0 0 7>;
443 interrupt-map = <0 0 0 1 &ipic 2 8
447 clock-frequency = <0>;
450 #address-cells = <3>;
454 ranges = <0x02000000 0 0xc8000000
455 0x02000000 0 0xc8000000
457 0x01000000 0 0x00000000
458 0x01000000 0 0x00000000