2 * MPC8378E MDS Device Tree Source
4 * Copyright 2007 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 model = "fsl,mpc8378emds";
16 compatible = "fsl,mpc8378emds","fsl,mpc837xmds";
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
40 i-cache-size = <32768>;
41 timebase-frequency = <0>;
43 clock-frequency = <0>;
48 device_type = "memory";
49 reg = <0x00000000 0x20000000>; // 512MB at 0
55 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
56 reg = <0xe0005000 0x1000>;
57 interrupts = <77 0x8>;
58 interrupt-parent = <&ipic>;
60 // booting from NOR flash
61 ranges = <0 0x0 0xfe000000 0x02000000
62 1 0x0 0xf8000000 0x00008000
63 3 0x0 0xe0600000 0x00008000>;
68 compatible = "cfi-flash";
69 reg = <0 0x0 0x2000000>;
79 reg = <0x100000 0x800000>;
83 reg = <0x1d00000 0x200000>;
87 reg = <0x1f00000 0x100000>;
93 compatible = "fsl,mpc837xmds-bcsr";
99 compatible = "fsl,mpc8378-fcm-nand",
101 reg = <3 0x0 0x8000>;
104 reg = <0x0 0x100000>;
109 reg = <0x100000 0x300000>;
113 reg = <0x400000 0x1c00000>;
119 #address-cells = <1>;
122 compatible = "simple-bus";
123 ranges = <0x0 0xe0000000 0x00100000>;
124 reg = <0xe0000000 0x00000200>;
128 compatible = "mpc83xx_wdt";
133 #address-cells = <1>;
135 compatible = "simple-bus";
136 sleep = <&pmc 0x0c000000>;
140 #address-cells = <1>;
143 compatible = "fsl-i2c";
144 reg = <0x3000 0x100>;
145 interrupts = <14 0x8>;
146 interrupt-parent = <&ipic>;
150 compatible = "dallas,ds1374";
152 interrupts = <19 0x8>;
153 interrupt-parent = <&ipic>;
158 compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
159 reg = <0x2e000 0x1000>;
160 interrupts = <42 0x8>;
161 interrupt-parent = <&ipic>;
162 /* Filled in by U-Boot */
163 clock-frequency = <0>;
168 #address-cells = <1>;
171 compatible = "fsl-i2c";
172 reg = <0x3100 0x100>;
173 interrupts = <15 0x8>;
174 interrupt-parent = <&ipic>;
180 compatible = "fsl,spi";
181 reg = <0x7000 0x1000>;
182 interrupts = <16 0x8>;
183 interrupt-parent = <&ipic>;
188 #address-cells = <1>;
190 compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
192 ranges = <0 0x8100 0x1a8>;
193 interrupt-parent = <&ipic>;
197 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
200 interrupt-parent = <&ipic>;
204 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
207 interrupt-parent = <&ipic>;
211 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
214 interrupt-parent = <&ipic>;
218 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
221 interrupt-parent = <&ipic>;
227 compatible = "fsl-usb2-dr";
228 reg = <0x23000 0x1000>;
229 #address-cells = <1>;
231 interrupt-parent = <&ipic>;
232 interrupts = <38 0x8>;
235 sleep = <&pmc 0x00c00000>;
239 #address-cells = <1>;
241 compatible = "fsl,gianfar-mdio";
242 reg = <0x24520 0x20>;
243 phy2: ethernet-phy@2 {
244 interrupt-parent = <&ipic>;
245 interrupts = <17 0x8>;
247 device_type = "ethernet-phy";
249 phy3: ethernet-phy@3 {
250 interrupt-parent = <&ipic>;
251 interrupts = <18 0x8>;
253 device_type = "ethernet-phy";
257 device_type = "tbi-phy";
262 #address-cells = <1>;
264 compatible = "fsl,gianfar-tbi";
265 reg = <0x25520 0x20>;
269 device_type = "tbi-phy";
274 enet0: ethernet@24000 {
276 device_type = "network";
278 compatible = "gianfar";
279 reg = <0x24000 0x1000>;
280 local-mac-address = [ 00 00 00 00 00 00 ];
281 interrupts = <32 0x8 33 0x8 34 0x8>;
282 phy-connection-type = "mii";
283 interrupt-parent = <&ipic>;
284 tbi-handle = <&tbi0>;
285 phy-handle = <&phy2>;
286 sleep = <&pmc 0xc0000000>;
290 enet1: ethernet@25000 {
292 device_type = "network";
294 compatible = "gianfar";
295 reg = <0x25000 0x1000>;
296 local-mac-address = [ 00 00 00 00 00 00 ];
297 interrupts = <35 0x8 36 0x8 37 0x8>;
298 phy-connection-type = "mii";
299 interrupt-parent = <&ipic>;
300 tbi-handle = <&tbi1>;
301 phy-handle = <&phy3>;
302 sleep = <&pmc 0x30000000>;
306 serial0: serial@4500 {
308 device_type = "serial";
309 compatible = "ns16550";
310 reg = <0x4500 0x100>;
311 clock-frequency = <0>;
312 interrupts = <9 0x8>;
313 interrupt-parent = <&ipic>;
316 serial1: serial@4600 {
318 device_type = "serial";
319 compatible = "ns16550";
320 reg = <0x4600 0x100>;
321 clock-frequency = <0>;
322 interrupts = <10 0x8>;
323 interrupt-parent = <&ipic>;
327 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
328 "fsl,sec2.1", "fsl,sec2.0";
329 reg = <0x30000 0x10000>;
330 interrupts = <11 0x8>;
331 interrupt-parent = <&ipic>;
332 fsl,num-channels = <4>;
333 fsl,channel-fifo-len = <24>;
334 fsl,exec-units-mask = <0x9fe>;
335 fsl,descriptor-types-mask = <0x3ab0ebf>;
336 sleep = <&pmc 0x03000000>;
340 * interrupts cell = <intr #, sense>
341 * sense values match linux IORESOURCE_IRQ_* defines:
342 * sense == 8: Level, low assertion
343 * sense == 2: Edge, high-to-low change
346 compatible = "fsl,ipic";
347 interrupt-controller;
348 #address-cells = <0>;
349 #interrupt-cells = <2>;
354 compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc";
355 reg = <0xb00 0x100 0xa00 0x100>;
356 interrupts = <80 0x8>;
357 interrupt-parent = <&ipic>;
363 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
367 0x8800 0x0 0x0 0x1 &ipic 20 0x8
368 0x8800 0x0 0x0 0x2 &ipic 21 0x8
369 0x8800 0x0 0x0 0x3 &ipic 22 0x8
370 0x8800 0x0 0x0 0x4 &ipic 23 0x8
373 0x9000 0x0 0x0 0x1 &ipic 22 0x8
374 0x9000 0x0 0x0 0x2 &ipic 23 0x8
375 0x9000 0x0 0x0 0x3 &ipic 20 0x8
376 0x9000 0x0 0x0 0x4 &ipic 21 0x8
379 0x9800 0x0 0x0 0x1 &ipic 23 0x8
380 0x9800 0x0 0x0 0x2 &ipic 20 0x8
381 0x9800 0x0 0x0 0x3 &ipic 21 0x8
382 0x9800 0x0 0x0 0x4 &ipic 22 0x8
385 0xa800 0x0 0x0 0x1 &ipic 20 0x8
386 0xa800 0x0 0x0 0x2 &ipic 21 0x8
387 0xa800 0x0 0x0 0x3 &ipic 22 0x8
388 0xa800 0x0 0x0 0x4 &ipic 23 0x8
391 0xb000 0x0 0x0 0x1 &ipic 23 0x8
392 0xb000 0x0 0x0 0x2 &ipic 20 0x8
393 0xb000 0x0 0x0 0x3 &ipic 21 0x8
394 0xb000 0x0 0x0 0x4 &ipic 22 0x8
397 0xb800 0x0 0x0 0x1 &ipic 22 0x8
398 0xb800 0x0 0x0 0x2 &ipic 23 0x8
399 0xb800 0x0 0x0 0x3 &ipic 20 0x8
400 0xb800 0x0 0x0 0x4 &ipic 21 0x8
403 0xc000 0x0 0x0 0x1 &ipic 21 0x8
404 0xc000 0x0 0x0 0x2 &ipic 22 0x8
405 0xc000 0x0 0x0 0x3 &ipic 23 0x8
406 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
407 interrupt-parent = <&ipic>;
408 interrupts = <66 0x8>;
409 bus-range = <0x0 0x0>;
410 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
411 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
412 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
413 clock-frequency = <0>;
414 sleep = <&pmc 0x00010000>;
415 #interrupt-cells = <1>;
417 #address-cells = <3>;
418 reg = <0xe0008500 0x100 /* internal registers */
419 0xe0008300 0x8>; /* config space access registers */
420 compatible = "fsl,mpc8349-pci";
424 pci1: pcie@e0009000 {
425 #address-cells = <3>;
427 #interrupt-cells = <1>;
429 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
430 reg = <0xe0009000 0x00001000>;
431 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
432 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
434 interrupt-map-mask = <0xf800 0 0 7>;
435 interrupt-map = <0 0 0 1 &ipic 1 8
439 sleep = <&pmc 0x00300000>;
440 clock-frequency = <0>;
443 #address-cells = <3>;
447 ranges = <0x02000000 0 0xa8000000
448 0x02000000 0 0xa8000000
450 0x01000000 0 0x00000000
451 0x01000000 0 0x00000000
456 pci2: pcie@e000a000 {
457 #address-cells = <3>;
459 #interrupt-cells = <1>;
461 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
462 reg = <0xe000a000 0x00001000>;
463 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
464 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
466 interrupt-map-mask = <0xf800 0 0 7>;
467 interrupt-map = <0 0 0 1 &ipic 2 8
471 sleep = <&pmc 0x000c0000>;
472 clock-frequency = <0>;
475 #address-cells = <3>;
479 ranges = <0x02000000 0 0xc8000000
480 0x02000000 0 0xc8000000
482 0x01000000 0 0x00000000
483 0x01000000 0 0x00000000