2 * MPC8377E RDB Device Tree Source
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 compatible = "fsl,mpc8377rdb";
36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <32768>;
39 i-cache-size = <32768>;
40 timebase-frequency = <0>;
42 clock-frequency = <0>;
47 device_type = "memory";
48 reg = <0x00000000 0x10000000>; // 256MB at 0
54 compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
55 reg = <0xe0005000 0x1000>;
56 interrupts = <77 0x8>;
57 interrupt-parent = <&ipic>;
59 // CS0 and CS1 are swapped when
60 // booting from nand, but the
61 // addresses are the same.
62 ranges = <0x0 0x0 0xfe000000 0x00800000
63 0x1 0x0 0xe0600000 0x00008000
64 0x2 0x0 0xf0000000 0x00020000
65 0x3 0x0 0xfa000000 0x00008000>;
70 compatible = "cfi-flash";
71 reg = <0x0 0x0 0x800000>;
79 compatible = "fsl,mpc8377-fcm-nand",
81 reg = <0x1 0x0 0x8000>;
89 reg = <0x100000 0x300000>;
92 reg = <0x400000 0x1c00000>;
101 compatible = "simple-bus";
102 ranges = <0x0 0xe0000000 0x00100000>;
103 reg = <0xe0000000 0x00000200>;
107 device_type = "watchdog";
108 compatible = "mpc83xx_wdt";
112 gpio1: gpio-controller@c00 {
114 compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
116 interrupts = <74 0x8>;
117 interrupt-parent = <&ipic>;
121 gpio2: gpio-controller@d00 {
123 compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
125 interrupts = <75 0x8>;
126 interrupt-parent = <&ipic>;
131 #address-cells = <1>;
133 compatible = "simple-bus";
134 sleep = <&pmc 0x0c000000>;
138 #address-cells = <1>;
141 compatible = "fsl-i2c";
142 reg = <0x3000 0x100>;
143 interrupts = <14 0x8>;
144 interrupt-parent = <&ipic>;
148 compatible = "national,lm75";
153 compatible = "at24,24c256";
158 compatible = "dallas,ds1339";
164 compatible = "fsl,mc9s08qg8-mpc8377erdb",
165 "fsl,mcu-mpc8349emitx";
172 compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
173 reg = <0x2e000 0x1000>;
174 interrupts = <42 0x8>;
175 interrupt-parent = <&ipic>;
176 /* Filled in by U-Boot */
177 clock-frequency = <0>;
182 #address-cells = <1>;
185 compatible = "fsl-i2c";
186 reg = <0x3100 0x100>;
187 interrupts = <15 0x8>;
188 interrupt-parent = <&ipic>;
194 compatible = "fsl,spi";
195 reg = <0x7000 0x1000>;
196 interrupts = <16 0x8>;
197 interrupt-parent = <&ipic>;
202 #address-cells = <1>;
204 compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
206 ranges = <0 0x8100 0x1a8>;
207 interrupt-parent = <&ipic>;
211 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
214 interrupt-parent = <&ipic>;
218 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
221 interrupt-parent = <&ipic>;
225 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
228 interrupt-parent = <&ipic>;
232 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
235 interrupt-parent = <&ipic>;
241 compatible = "fsl-usb2-dr";
242 reg = <0x23000 0x1000>;
243 #address-cells = <1>;
245 interrupt-parent = <&ipic>;
246 interrupts = <38 0x8>;
248 sleep = <&pmc 0x00c00000>;
252 #address-cells = <1>;
254 compatible = "fsl,gianfar-mdio";
255 reg = <0x24520 0x20>;
256 phy2: ethernet-phy@2 {
257 interrupt-parent = <&ipic>;
258 interrupts = <17 0x8>;
260 device_type = "ethernet-phy";
264 device_type = "tbi-phy";
269 #address-cells = <1>;
271 compatible = "fsl,gianfar-tbi";
272 reg = <0x25520 0x20>;
276 device_type = "tbi-phy";
281 enet0: ethernet@24000 {
283 device_type = "network";
285 compatible = "gianfar";
286 reg = <0x24000 0x1000>;
287 local-mac-address = [ 00 00 00 00 00 00 ];
288 interrupts = <32 0x8 33 0x8 34 0x8>;
289 phy-connection-type = "mii";
290 interrupt-parent = <&ipic>;
291 tbi-handle = <&tbi0>;
292 phy-handle = <&phy2>;
293 sleep = <&pmc 0xc0000000>;
297 enet1: ethernet@25000 {
299 device_type = "network";
301 compatible = "gianfar";
302 reg = <0x25000 0x1000>;
303 local-mac-address = [ 00 00 00 00 00 00 ];
304 interrupts = <35 0x8 36 0x8 37 0x8>;
305 phy-connection-type = "mii";
306 interrupt-parent = <&ipic>;
307 fixed-link = <1 1 1000 0 0>;
308 tbi-handle = <&tbi1>;
309 sleep = <&pmc 0x30000000>;
313 serial0: serial@4500 {
315 device_type = "serial";
316 compatible = "ns16550";
317 reg = <0x4500 0x100>;
318 clock-frequency = <0>;
319 interrupts = <9 0x8>;
320 interrupt-parent = <&ipic>;
323 serial1: serial@4600 {
325 device_type = "serial";
326 compatible = "ns16550";
327 reg = <0x4600 0x100>;
328 clock-frequency = <0>;
329 interrupts = <10 0x8>;
330 interrupt-parent = <&ipic>;
334 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
335 "fsl,sec2.1", "fsl,sec2.0";
336 reg = <0x30000 0x10000>;
337 interrupts = <11 0x8>;
338 interrupt-parent = <&ipic>;
339 fsl,num-channels = <4>;
340 fsl,channel-fifo-len = <24>;
341 fsl,exec-units-mask = <0x9fe>;
342 fsl,descriptor-types-mask = <0x3ab0ebf>;
343 sleep = <&pmc 0x03000000>;
347 compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
348 reg = <0x18000 0x1000>;
349 interrupts = <44 0x8>;
350 interrupt-parent = <&ipic>;
351 sleep = <&pmc 0x000000c0>;
355 compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
356 reg = <0x19000 0x1000>;
357 interrupts = <45 0x8>;
358 interrupt-parent = <&ipic>;
359 sleep = <&pmc 0x00000030>;
363 * interrupts cell = <intr #, sense>
364 * sense values match linux IORESOURCE_IRQ_* defines:
365 * sense == 8: Level, low assertion
366 * sense == 2: Edge, high-to-low change
368 ipic: interrupt-controller@700 {
369 compatible = "fsl,ipic";
370 interrupt-controller;
371 #address-cells = <0>;
372 #interrupt-cells = <2>;
377 compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
378 reg = <0xb00 0x100 0xa00 0x100>;
379 interrupts = <80 0x8>;
380 interrupt-parent = <&ipic>;
385 interrupt-map-mask = <0xf800 0 0 7>;
387 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
389 /* IDSEL AD14 IRQ6 inta */
390 0x7000 0x0 0x0 0x1 &ipic 22 0x8
392 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
393 0x7800 0x0 0x0 0x1 &ipic 21 0x8
394 0x7800 0x0 0x0 0x2 &ipic 22 0x8
395 0x7800 0x0 0x0 0x4 &ipic 23 0x8
397 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
398 0xE000 0x0 0x0 0x1 &ipic 23 0x8
399 0xE000 0x0 0x0 0x2 &ipic 21 0x8
400 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
401 interrupt-parent = <&ipic>;
402 interrupts = <66 0x8>;
404 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
405 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
406 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
407 sleep = <&pmc 0x00010000>;
408 clock-frequency = <66666666>;
409 #interrupt-cells = <1>;
411 #address-cells = <3>;
412 reg = <0xe0008500 0x100 /* internal registers */
413 0xe0008300 0x8>; /* config space access registers */
414 compatible = "fsl,mpc8349-pci";
418 pci1: pcie@e0009000 {
419 #address-cells = <3>;
421 #interrupt-cells = <1>;
423 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
424 reg = <0xe0009000 0x00001000>;
425 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
426 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
428 interrupt-map-mask = <0xf800 0 0 7>;
429 interrupt-map = <0 0 0 1 &ipic 1 8
433 sleep = <&pmc 0x00300000>;
434 clock-frequency = <0>;
437 #address-cells = <3>;
441 ranges = <0x02000000 0 0xa8000000
442 0x02000000 0 0xa8000000
444 0x01000000 0 0x00000000
445 0x01000000 0 0x00000000
450 pci2: pcie@e000a000 {
451 #address-cells = <3>;
453 #interrupt-cells = <1>;
455 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
456 reg = <0xe000a000 0x00001000>;
457 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
458 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
460 interrupt-map-mask = <0xf800 0 0 7>;
461 interrupt-map = <0 0 0 1 &ipic 2 8
465 sleep = <&pmc 0x000c0000>;
466 clock-frequency = <0>;
469 #address-cells = <3>;
473 ranges = <0x02000000 0 0xc8000000
474 0x02000000 0 0xc8000000
476 0x01000000 0 0x00000000
477 0x01000000 0 0x00000000