2 * MPC8360E EMDS Device Tree Source
4 * Copyright 2006 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
14 /memreserve/ 00000000 1000000;
21 compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <32768>; // L1, 32K
43 i-cache-size = <32768>; // L1, 32K
44 timebase-frequency = <66000000>;
45 bus-frequency = <264000000>;
46 clock-frequency = <528000000>;
51 device_type = "memory";
52 reg = <0x00000000 0x10000000>;
58 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
60 reg = <0xe0005000 0xd8>;
61 ranges = <0 0 0xfe000000 0x02000000
62 1 0 0xf8000000 0x00008000>;
65 compatible = "cfi-flash";
66 reg = <0 0 0x2000000>;
72 device_type = "board-control";
81 compatible = "simple-bus";
82 ranges = <0x0 0xe0000000 0x00100000>;
83 reg = <0xe0000000 0x00000200>;
84 bus-frequency = <264000000>;
87 device_type = "watchdog";
88 compatible = "mpc83xx_wdt";
96 compatible = "fsl-i2c";
98 interrupts = <14 0x8>;
99 interrupt-parent = <&ipic>;
103 compatible = "dallas,ds1374";
109 #address-cells = <1>;
112 compatible = "fsl-i2c";
113 reg = <0x3100 0x100>;
114 interrupts = <15 0x8>;
115 interrupt-parent = <&ipic>;
119 serial0: serial@4500 {
121 device_type = "serial";
122 compatible = "ns16550";
123 reg = <0x4500 0x100>;
124 clock-frequency = <264000000>;
125 interrupts = <9 0x8>;
126 interrupt-parent = <&ipic>;
129 serial1: serial@4600 {
131 device_type = "serial";
132 compatible = "ns16550";
133 reg = <0x4600 0x100>;
134 clock-frequency = <264000000>;
135 interrupts = <10 0x8>;
136 interrupt-parent = <&ipic>;
140 #address-cells = <1>;
142 compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
144 ranges = <0 0x8100 0x1a8>;
145 interrupt-parent = <&ipic>;
149 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
151 interrupt-parent = <&ipic>;
155 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
157 interrupt-parent = <&ipic>;
161 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
163 interrupt-parent = <&ipic>;
167 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
169 interrupt-parent = <&ipic>;
175 compatible = "fsl,sec2.0";
176 reg = <0x30000 0x10000>;
177 interrupts = <11 0x8>;
178 interrupt-parent = <&ipic>;
179 fsl,num-channels = <4>;
180 fsl,channel-fifo-len = <24>;
181 fsl,exec-units-mask = <0x7e>;
182 fsl,descriptor-types-mask = <0x01010ebf>;
186 interrupt-controller;
187 #address-cells = <0>;
188 #interrupt-cells = <2>;
190 device_type = "ipic";
194 reg = <0x1400 0x100>;
195 device_type = "par_io";
200 /* port pin dir open_drain assignment has_irq */
201 0 3 1 0 1 0 /* TxD0 */
202 0 4 1 0 1 0 /* TxD1 */
203 0 5 1 0 1 0 /* TxD2 */
204 0 6 1 0 1 0 /* TxD3 */
205 1 6 1 0 3 0 /* TxD4 */
206 1 7 1 0 1 0 /* TxD5 */
207 1 9 1 0 2 0 /* TxD6 */
208 1 10 1 0 2 0 /* TxD7 */
209 0 9 2 0 1 0 /* RxD0 */
210 0 10 2 0 1 0 /* RxD1 */
211 0 11 2 0 1 0 /* RxD2 */
212 0 12 2 0 1 0 /* RxD3 */
213 0 13 2 0 1 0 /* RxD4 */
214 1 1 2 0 2 0 /* RxD5 */
215 1 0 2 0 2 0 /* RxD6 */
216 1 4 2 0 2 0 /* RxD7 */
217 0 7 1 0 1 0 /* TX_EN */
218 0 8 1 0 1 0 /* TX_ER */
219 0 15 2 0 1 0 /* RX_DV */
220 0 16 2 0 1 0 /* RX_ER */
221 0 0 2 0 1 0 /* RX_CLK */
222 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
223 2 8 2 0 1 0>; /* GTX125 - CLK9 */
227 /* port pin dir open_drain assignment has_irq */
228 0 17 1 0 1 0 /* TxD0 */
229 0 18 1 0 1 0 /* TxD1 */
230 0 19 1 0 1 0 /* TxD2 */
231 0 20 1 0 1 0 /* TxD3 */
232 1 2 1 0 1 0 /* TxD4 */
233 1 3 1 0 2 0 /* TxD5 */
234 1 5 1 0 3 0 /* TxD6 */
235 1 8 1 0 3 0 /* TxD7 */
236 0 23 2 0 1 0 /* RxD0 */
237 0 24 2 0 1 0 /* RxD1 */
238 0 25 2 0 1 0 /* RxD2 */
239 0 26 2 0 1 0 /* RxD3 */
240 0 27 2 0 1 0 /* RxD4 */
241 1 12 2 0 2 0 /* RxD5 */
242 1 13 2 0 3 0 /* RxD6 */
243 1 11 2 0 2 0 /* RxD7 */
244 0 21 1 0 1 0 /* TX_EN */
245 0 22 1 0 1 0 /* TX_ER */
246 0 29 2 0 1 0 /* RX_DV */
247 0 30 2 0 1 0 /* RX_ER */
248 0 31 2 0 1 0 /* RX_CLK */
249 2 2 1 0 2 0 /* GTX_CLK - CLK10 */
250 2 3 2 0 1 0 /* GTX125 - CLK4 */
251 0 1 3 0 2 0 /* MDIO */
252 0 2 1 0 1 0>; /* MDC */
259 #address-cells = <1>;
262 compatible = "fsl,qe";
263 ranges = <0x0 0xe0100000 0x00100000>;
264 reg = <0xe0100000 0x480>;
266 bus-frequency = <396000000>;
269 #address-cells = <1>;
271 compatible = "fsl,qe-muram", "fsl,cpm-muram";
272 ranges = <0x0 0x00010000 0x0000c000>;
275 compatible = "fsl,qe-muram-data",
276 "fsl,cpm-muram-data";
283 compatible = "fsl,spi";
286 interrupt-parent = <&qeic>;
292 compatible = "fsl,spi";
295 interrupt-parent = <&qeic>;
300 compatible = "qe_udc";
301 reg = <0x6c0 0x40 0x8b00 0x100>;
303 interrupt-parent = <&qeic>;
308 device_type = "network";
309 compatible = "ucc_geth";
311 reg = <0x2000 0x200>;
313 interrupt-parent = <&qeic>;
314 local-mac-address = [ 00 00 00 00 00 00 ];
315 rx-clock-name = "none";
316 tx-clock-name = "clk9";
317 phy-handle = <&phy0>;
318 phy-connection-type = "rgmii-id";
319 pio-handle = <&pio1>;
323 device_type = "network";
324 compatible = "ucc_geth";
326 reg = <0x3000 0x200>;
328 interrupt-parent = <&qeic>;
329 local-mac-address = [ 00 00 00 00 00 00 ];
330 rx-clock-name = "none";
331 tx-clock-name = "clk4";
332 phy-handle = <&phy1>;
333 phy-connection-type = "rgmii-id";
334 pio-handle = <&pio2>;
338 #address-cells = <1>;
341 compatible = "fsl,ucc-mdio";
343 phy0: ethernet-phy@00 {
344 interrupt-parent = <&ipic>;
345 interrupts = <17 0x8>;
347 device_type = "ethernet-phy";
349 phy1: ethernet-phy@01 {
350 interrupt-parent = <&ipic>;
351 interrupts = <18 0x8>;
353 device_type = "ethernet-phy";
357 qeic: interrupt-controller@80 {
358 interrupt-controller;
359 compatible = "fsl,qe-ic";
360 #address-cells = <0>;
361 #interrupt-cells = <1>;
364 interrupts = <32 0x8 33 0x8>; // high:32 low:33
365 interrupt-parent = <&ipic>;
371 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
374 /* IDSEL 0x11 AD17 */
375 0x8800 0x0 0x0 0x1 &ipic 20 0x8
376 0x8800 0x0 0x0 0x2 &ipic 21 0x8
377 0x8800 0x0 0x0 0x3 &ipic 22 0x8
378 0x8800 0x0 0x0 0x4 &ipic 23 0x8
380 /* IDSEL 0x12 AD18 */
381 0x9000 0x0 0x0 0x1 &ipic 22 0x8
382 0x9000 0x0 0x0 0x2 &ipic 23 0x8
383 0x9000 0x0 0x0 0x3 &ipic 20 0x8
384 0x9000 0x0 0x0 0x4 &ipic 21 0x8
386 /* IDSEL 0x13 AD19 */
387 0x9800 0x0 0x0 0x1 &ipic 23 0x8
388 0x9800 0x0 0x0 0x2 &ipic 20 0x8
389 0x9800 0x0 0x0 0x3 &ipic 21 0x8
390 0x9800 0x0 0x0 0x4 &ipic 22 0x8
393 0xa800 0x0 0x0 0x1 &ipic 20 0x8
394 0xa800 0x0 0x0 0x2 &ipic 21 0x8
395 0xa800 0x0 0x0 0x3 &ipic 22 0x8
396 0xa800 0x0 0x0 0x4 &ipic 23 0x8
399 0xb000 0x0 0x0 0x1 &ipic 23 0x8
400 0xb000 0x0 0x0 0x2 &ipic 20 0x8
401 0xb000 0x0 0x0 0x3 &ipic 21 0x8
402 0xb000 0x0 0x0 0x4 &ipic 22 0x8
405 0xb800 0x0 0x0 0x1 &ipic 22 0x8
406 0xb800 0x0 0x0 0x2 &ipic 23 0x8
407 0xb800 0x0 0x0 0x3 &ipic 20 0x8
408 0xb800 0x0 0x0 0x4 &ipic 21 0x8
411 0xc000 0x0 0x0 0x1 &ipic 21 0x8
412 0xc000 0x0 0x0 0x2 &ipic 22 0x8
413 0xc000 0x0 0x0 0x3 &ipic 23 0x8
414 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
415 interrupt-parent = <&ipic>;
416 interrupts = <66 0x8>;
418 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
419 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
420 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
421 clock-frequency = <66666666>;
422 #interrupt-cells = <1>;
424 #address-cells = <3>;
425 reg = <0xe0008500 0x100>;
426 compatible = "fsl,mpc8349-pci";