2 * MPC832x RDB Device Tree Source
4 * Copyright 2007 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 model = "MPC8323ERDB";
16 compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
35 d-cache-line-size = <0x20>; // 32 bytes
36 i-cache-line-size = <0x20>; // 32 bytes
37 d-cache-size = <16384>; // L1, 16K
38 i-cache-size = <16384>; // L1, 16K
39 timebase-frequency = <0>;
41 clock-frequency = <0>;
46 device_type = "memory";
47 reg = <0x00000000 0x04000000>;
54 ranges = <0x0 0xe0000000 0x00100000>;
55 reg = <0xe0000000 0x00000200>;
59 device_type = "watchdog";
60 compatible = "mpc83xx_wdt";
68 compatible = "fsl-i2c";
70 interrupts = <14 0x8>;
71 interrupt-parent = <&ipic>;
75 serial0: serial@4500 {
77 device_type = "serial";
78 compatible = "ns16550";
80 clock-frequency = <0>;
82 interrupt-parent = <&ipic>;
85 serial1: serial@4600 {
87 device_type = "serial";
88 compatible = "ns16550";
90 clock-frequency = <0>;
91 interrupts = <10 0x8>;
92 interrupt-parent = <&ipic>;
98 compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
100 ranges = <0 0x8100 0x1a8>;
101 interrupt-parent = <&ipic>;
105 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
107 interrupt-parent = <&ipic>;
111 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
113 interrupt-parent = <&ipic>;
117 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
119 interrupt-parent = <&ipic>;
123 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
125 interrupt-parent = <&ipic>;
131 device_type = "crypto";
133 compatible = "talitos";
134 reg = <0x30000 0x7000>;
135 interrupts = <11 0x8>;
136 interrupt-parent = <&ipic>;
139 channel-fifo-len = <24>;
140 exec-units-mask = <0x0000004c>;
141 descriptor-types-mask = <0x0122003f>;
145 interrupt-controller;
146 #address-cells = <0>;
147 #interrupt-cells = <2>;
149 device_type = "ipic";
153 reg = <0x1400 0x100>;
154 device_type = "par_io";
159 /* port pin dir open_drain assignment has_irq */
160 3 4 3 0 2 0 /* MDIO */
161 3 5 1 0 2 0 /* MDC */
162 3 21 2 0 1 0 /* RX_CLK (CLK16) */
163 3 23 2 0 1 0 /* TX_CLK (CLK3) */
164 0 18 1 0 1 0 /* TxD0 */
165 0 19 1 0 1 0 /* TxD1 */
166 0 20 1 0 1 0 /* TxD2 */
167 0 21 1 0 1 0 /* TxD3 */
168 0 22 2 0 1 0 /* RxD0 */
169 0 23 2 0 1 0 /* RxD1 */
170 0 24 2 0 1 0 /* RxD2 */
171 0 25 2 0 1 0 /* RxD3 */
172 0 26 2 0 1 0 /* RX_ER */
173 0 27 1 0 1 0 /* TX_ER */
174 0 28 2 0 1 0 /* RX_DV */
175 0 29 2 0 1 0 /* COL */
176 0 30 1 0 1 0 /* TX_EN */
177 0 31 2 0 1 0>; /* CRS */
181 /* port pin dir open_drain assignment has_irq */
182 0 13 2 0 1 0 /* RX_CLK (CLK9) */
183 3 24 2 0 1 0 /* TX_CLK (CLK10) */
184 1 0 1 0 1 0 /* TxD0 */
185 1 1 1 0 1 0 /* TxD1 */
186 1 2 1 0 1 0 /* TxD2 */
187 1 3 1 0 1 0 /* TxD3 */
188 1 4 2 0 1 0 /* RxD0 */
189 1 5 2 0 1 0 /* RxD1 */
190 1 6 2 0 1 0 /* RxD2 */
191 1 7 2 0 1 0 /* RxD3 */
192 1 8 2 0 1 0 /* RX_ER */
193 1 9 1 0 1 0 /* TX_ER */
194 1 10 2 0 1 0 /* RX_DV */
195 1 11 2 0 1 0 /* COL */
196 1 12 1 0 1 0 /* TX_EN */
197 1 13 2 0 1 0>; /* CRS */
203 #address-cells = <1>;
206 compatible = "fsl,qe";
207 ranges = <0x0 0xe0100000 0x00100000>;
208 reg = <0xe0100000 0x480>;
210 bus-frequency = <198000000>;
213 #address-cells = <1>;
215 compatible = "fsl,qe-muram", "fsl,cpm-muram";
216 ranges = <0x0 0x00010000 0x00004000>;
219 compatible = "fsl,qe-muram-data",
220 "fsl,cpm-muram-data";
227 compatible = "fsl,spi";
230 interrupt-parent = <&qeic>;
236 compatible = "fsl,spi";
239 interrupt-parent = <&qeic>;
244 device_type = "network";
245 compatible = "ucc_geth";
247 reg = <0x3000 0x200>;
249 interrupt-parent = <&qeic>;
250 local-mac-address = [ 00 00 00 00 00 00 ];
251 rx-clock-name = "clk16";
252 tx-clock-name = "clk3";
253 phy-handle = <&phy00>;
254 pio-handle = <&ucc2pio>;
258 device_type = "network";
259 compatible = "ucc_geth";
261 reg = <0x2200 0x200>;
263 interrupt-parent = <&qeic>;
264 local-mac-address = [ 00 00 00 00 00 00 ];
265 rx-clock-name = "clk9";
266 tx-clock-name = "clk10";
267 phy-handle = <&phy04>;
268 pio-handle = <&ucc3pio>;
272 #address-cells = <1>;
275 compatible = "fsl,ucc-mdio";
277 phy00:ethernet-phy@00 {
278 interrupt-parent = <&ipic>;
281 device_type = "ethernet-phy";
283 phy04:ethernet-phy@04 {
284 interrupt-parent = <&ipic>;
287 device_type = "ethernet-phy";
291 qeic:interrupt-controller@80 {
292 interrupt-controller;
293 compatible = "fsl,qe-ic";
294 #address-cells = <0>;
295 #interrupt-cells = <1>;
298 interrupts = <32 0x8 33 0x8>; //high:32 low:33
299 interrupt-parent = <&ipic>;
305 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
307 /* IDSEL 0x10 AD16 (USB) */
308 0x8000 0x0 0x0 0x1 &ipic 17 0x8
310 /* IDSEL 0x11 AD17 (Mini1)*/
311 0x8800 0x0 0x0 0x1 &ipic 18 0x8
312 0x8800 0x0 0x0 0x2 &ipic 19 0x8
313 0x8800 0x0 0x0 0x3 &ipic 20 0x8
314 0x8800 0x0 0x0 0x4 &ipic 48 0x8
316 /* IDSEL 0x12 AD18 (PCI/Mini2) */
317 0x9000 0x0 0x0 0x1 &ipic 19 0x8
318 0x9000 0x0 0x0 0x2 &ipic 20 0x8
319 0x9000 0x0 0x0 0x3 &ipic 48 0x8
320 0x9000 0x0 0x0 0x4 &ipic 17 0x8>;
322 interrupt-parent = <&ipic>;
323 interrupts = <66 0x8>;
324 bus-range = <0x0 0x0>;
325 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
326 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
327 0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
328 clock-frequency = <0>;
329 #interrupt-cells = <1>;
331 #address-cells = <3>;
332 reg = <0xe0008500 0x100>;
333 compatible = "fsl,mpc8349-pci";