arch/powerpc/boot/dts/gef_sbc610.dts

   1 /*
   2  * GE Fanuc SBC610 Device Tree Source
   3  *
   4  * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  *
  11  * Based on: SBS CM6 Device Tree Source
  12  * Copyright 2007 SBS Technologies GmbH & Co. KG
  13  * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
  14  * Copyright 2006 Freescale Semiconductor Inc.
  15  */
  16
  17 /*
  18  * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
  19  */
  20
  21 /dts-v1/;
  22
  23 / {
  24         model = "GEF_SBC610";
  25         compatible = "gef,sbc610";
  26         #address-cells = <1>;
  27         #size-cells = <1>;
  28
  29         aliases {
  30                 ethernet0 = &enet0;
  31                 ethernet1 = &enet1;
  32                 serial0 = &serial0;
  33                 serial1 = &serial1;
  34                 pci0 = &pci0;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 PowerPC,8641@0 {
  42                         device_type = "cpu";
  43                         reg = <0>;
  44                         d-cache-line-size = <32>;       // 32 bytes
  45                         i-cache-line-size = <32>;       // 32 bytes
  46                         d-cache-size = <32768>;         // L1, 32K
  47                         i-cache-size = <32768>;         // L1, 32K
  48                         timebase-frequency = <0>;       // From uboot
  49                         bus-frequency = <0>;            // From uboot
  50                         clock-frequency = <0>;          // From uboot
  51                 };
  52                 PowerPC,8641@1 {
  53                         device_type = "cpu";
  54                         reg = <1>;
  55                         d-cache-line-size = <32>;       // 32 bytes
  56                         i-cache-line-size = <32>;       // 32 bytes
  57                         d-cache-size = <32768>;         // L1, 32K
  58                         i-cache-size = <32768>;         // L1, 32K
  59                         timebase-frequency = <0>;       // From uboot
  60                         bus-frequency = <0>;            // From uboot
  61                         clock-frequency = <0>;          // From uboot
  62                 };
  63         };
  64
  65         memory {
  66                 device_type = "memory";
  67                 reg = <0x0 0x40000000>; // set by uboot
  68         };
  69
  70         localbus@fef05000 {
  71                 #address-cells = <2>;
  72                 #size-cells = <1>;
  73                 compatible = "fsl,mpc8641-localbus", "simple-bus";
  74                 reg = <0xf8005000 0x1000>;
  75                 interrupts = <19 2>;
  76                 interrupt-parent = <&mpic>;
  77
  78                 ranges = <0 0 0xff000000 0x01000000     // 16MB Boot flash
  79                           1 0 0xe8000000 0x08000000     // Paged Flash 0
  80                           2 0 0xe0000000 0x08000000     // Paged Flash 1
  81                           3 0 0xfc100000 0x00020000     // NVRAM
  82                           4 0 0xfc000000 0x00008000     // FPGA
  83                           5 0 0xfc008000 0x00008000     // AFIX FPGA
  84                           6 0 0xfd000000 0x00800000     // IO FPGA (8-bit)
  85                           7 0 0xfd800000 0x00800000>;   // IO FPGA (32-bit)
  86
  87                 fpga@4,0 {
  88                         compatible = "gef,fpga-regs";
  89                         reg = <0x4 0x0 0x40>;
  90                 };
  91                 gef_pic: pic@4,4000 {
  92                         #interrupt-cells = <1>;
  93                         interrupt-controller;
  94                         compatible = "gef,fpga-pic";
  95                         reg = <0x4 0x4000 0x20>;
  96                         interrupts = <0x8
  97                                       0x9>;
  98                         interrupt-parent = <&mpic>;
  99
 100                 };
 101         };
 102
 103         soc@fef00000 {
 104                 #address-cells = <1>;
 105                 #size-cells = <1>;
 106                 #interrupt-cells = <2>;
 107                 device_type = "soc";
 108                 compatible = "simple-bus";
 109                 ranges = <0x0 0xfef00000 0x00100000>;
 110                 reg = <0xfef00000 0x100000>;    // CCSRBAR 1M
 111                 bus-frequency = <33333333>;
 112
 113                 i2c1: i2c@3000 {
 114                         #address-cells = <1>;
 115                         #size-cells = <0>;
 116                         compatible = "fsl-i2c";
 117                         reg = <0x3000 0x100>;
 118                         interrupts = <0x2b 0x2>;
 119                         interrupt-parent = <&mpic>;
 120                         dfsrr;
 121
 122                         eti@6b {
 123                                 compatible = "dallas,ds1682";
 124                                 reg = <0x6b>;
 125                         };
 126                 };
 127
 128                 i2c2: i2c@3100 {
 129                         #address-cells = <1>;
 130                         #size-cells = <0>;
 131                         compatible = "fsl-i2c";
 132                         reg = <0x3100 0x100>;
 133                         interrupts = <0x2b 0x2>;
 134                         interrupt-parent = <&mpic>;
 135                         dfsrr;
 136                 };
 137
 138                 dma@21300 {
 139                         #address-cells = <1>;
 140                         #size-cells = <1>;
 141                         compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
 142                         reg = <0x21300 0x4>;
 143                         ranges = <0x0 0x21100 0x200>;
 144                         cell-index = <0>;
 145                         dma-channel@0 {
 146                                 compatible = "fsl,mpc8641-dma-channel",
 147                                            "fsl,eloplus-dma-channel";
 148                                 reg = <0x0 0x80>;
 149                                 cell-index = <0>;
 150                                 interrupt-parent = <&mpic>;
 151                                 interrupts = <20 2>;
 152                         };
 153                         dma-channel@80 {
 154                                 compatible = "fsl,mpc8641-dma-channel",
 155                                            "fsl,eloplus-dma-channel";
 156                                 reg = <0x80 0x80>;
 157                                 cell-index = <1>;
 158                                 interrupt-parent = <&mpic>;
 159                                 interrupts = <21 2>;
 160                         };
 161                         dma-channel@100 {
 162                                 compatible = "fsl,mpc8641-dma-channel",
 163                                            "fsl,eloplus-dma-channel";
 164                                 reg = <0x100 0x80>;
 165                                 cell-index = <2>;
 166                                 interrupt-parent = <&mpic>;
 167                                 interrupts = <22 2>;
 168                         };
 169                         dma-channel@180 {
 170                                 compatible = "fsl,mpc8641-dma-channel",
 171                                            "fsl,eloplus-dma-channel";
 172                                 reg = <0x180 0x80>;
 173                                 cell-index = <3>;
 174                                 interrupt-parent = <&mpic>;
 175                                 interrupts = <23 2>;
 176                         };
 177                 };
 178
 179                 mdio@24520 {
 180                         #address-cells = <1>;
 181                         #size-cells = <0>;
 182                         compatible = "fsl,gianfar-mdio";
 183                         reg = <0x24520 0x20>;
 184
 185                         phy0: ethernet-phy@0 {
 186                                 interrupt-parent = <&gef_pic>;
 187                                 interrupts = <0x9 0x4>;
 188                                 reg = <1>;
 189                         };
 190                         phy2: ethernet-phy@2 {
 191                                 interrupt-parent = <&gef_pic>;
 192                                 interrupts = <0x8 0x4>;
 193                                 reg = <3>;
 194                         };
 195                 };
 196
 197                 enet0: ethernet@24000 {
 198                         device_type = "network";
 199                         model = "eTSEC";
 200                         compatible = "gianfar";
 201                         reg = <0x24000 0x1000>;
 202                         local-mac-address = [ 00 00 00 00 00 00 ];
 203                         interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
 204                         interrupt-parent = <&mpic>;
 205                         phy-handle = <&phy0>;
 206                         phy-connection-type = "gmii";
 207                 };
 208
 209                 enet1: ethernet@26000 {
 210                         device_type = "network";
 211                         model = "eTSEC";
 212                         compatible = "gianfar";
 213                         reg = <0x26000 0x1000>;
 214                         local-mac-address = [ 00 00 00 00 00 00 ];
 215                         interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
 216                         interrupt-parent = <&mpic>;
 217                         phy-handle = <&phy2>;
 218                         phy-connection-type = "gmii";
 219                 };
 220
 221                 serial0: serial@4500 {
 222                         cell-index = <0>;
 223                         device_type = "serial";
 224                         compatible = "ns16550";
 225                         reg = <0x4500 0x100>;
 226                         clock-frequency = <0>;
 227                         interrupts = <0x2a 0x2>;
 228                         interrupt-parent = <&mpic>;
 229                 };
 230
 231                 serial1: serial@4600 {
 232                         cell-index = <1>;
 233                         device_type = "serial";
 234                         compatible = "ns16550";
 235                         reg = <0x4600 0x100>;
 236                         clock-frequency = <0>;
 237                         interrupts = <0x1c 0x2>;
 238                         interrupt-parent = <&mpic>;
 239                 };
 240
 241                 mpic: pic@40000 {
 242                         clock-frequency = <0>;
 243                         interrupt-controller;
 244                         #address-cells = <0>;
 245                         #interrupt-cells = <2>;
 246                         reg = <0x40000 0x40000>;
 247                         compatible = "chrp,open-pic";
 248                         device_type = "open-pic";
 249                 };
 250
 251                 global-utilities@e0000 {
 252                         compatible = "fsl,mpc8641-guts";
 253                         reg = <0xe0000 0x1000>;
 254                         fsl,has-rstcr;
 255                 };
 256         };
 257
 258         pci0: pcie@fef08000 {
 259                 compatible = "fsl,mpc8641-pcie";
 260                 device_type = "pci";
 261                 #interrupt-cells = <1>;
 262                 #size-cells = <2>;
 263                 #address-cells = <3>;
 264                 reg = <0xfef08000 0x1000>;
 265                 bus-range = <0x0 0xff>;
 266                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
 267                           0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
 268                 clock-frequency = <33333333>;
 269                 interrupt-parent = <&mpic>;
 270                 interrupts = <0x18 0x2>;
 271                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 272                 interrupt-map = <
 273                         0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
 274                         0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
 275                         0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
 276                         0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
 277                 >;
 278
 279                 pcie@0 {
 280                         reg = <0 0 0 0 0>;
 281                         #size-cells = <2>;
 282                         #address-cells = <3>;
 283                         device_type = "pci";
 284                         ranges = <0x02000000 0x0 0x80000000
 285                                   0x02000000 0x0 0x80000000
 286                                   0x0 0x40000000
 287
 288                                   0x01000000 0x0 0x00000000
 289                                   0x01000000 0x0 0x00000000
 290                                   0x0 0x00400000>;
 291                 };
 292         };
 293 };