1 /* MN10300 Misalignment fixup handler
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
11 #include <linux/module.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/errno.h>
16 #include <linux/ptrace.h>
17 #include <linux/timer.h>
19 #include <linux/smp.h>
20 #include <linux/smp_lock.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/pci.h>
26 #include <asm/processor.h>
27 #include <asm/system.h>
28 #include <asm/uaccess.h>
30 #include <asm/atomic.h>
32 #include <asm/pgalloc.h>
33 #include <asm/cpu-regs.h>
34 #include <asm/busctl-regs.h>
36 #include <asm/gdb-stub.h>
37 #include <asm/asm-offsets.h>
40 #define kdebug(FMT, ...) printk(KERN_DEBUG "MISALIGN: "FMT"\n", ##__VA_ARGS__)
42 #define kdebug(FMT, ...) do {} while (0)
45 static int misalignment_addr(unsigned long *registers, unsigned params,
46 unsigned opcode, unsigned disp,
47 void **_address, unsigned long **_postinc);
49 static int misalignment_reg(unsigned long *registers, unsigned params,
50 unsigned opcode, unsigned disp,
51 unsigned long **_register);
53 static const unsigned Dreg_index[] = {
54 REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
57 static const unsigned Areg_index[] = {
58 REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2
61 static const unsigned Rreg_index[] = {
62 REG_E0 >> 2, REG_E1 >> 2, REG_E2 >> 2, REG_E3 >> 2,
63 REG_E4 >> 2, REG_E5 >> 2, REG_E6 >> 2, REG_E7 >> 2,
64 REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2,
65 REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
84 u_int8_t opsz, dispsz;
92 [FMT_D2] = { 16, 16 },
93 [FMT_D4] = { 16, 32 },
96 [FMT_D8] = { 24, 24 },
97 [FMT_D9] = { 24, 32 },
101 DM0, /* data reg in opcode in bits 0-1 */
102 DM1, /* data reg in opcode in bits 2-3 */
103 DM2, /* data reg in opcode in bits 4-5 */
104 AM0, /* addr reg in opcode in bits 0-1 */
105 AM1, /* addr reg in opcode in bits 2-3 */
106 AM2, /* addr reg in opcode in bits 4-5 */
107 RM0, /* reg in opcode in bits 0-3 */
108 RM1, /* reg in opcode in bits 2-5 */
109 RM2, /* reg in opcode in bits 4-7 */
110 RM4, /* reg in opcode in bits 8-11 */
111 RM6, /* reg in opcode in bits 12-15 */
113 RD0, /* reg in displacement in bits 0-3 */
114 RD2, /* reg in displacement in bits 4-7 */
116 SP, /* stack pointer */
118 SD8, /* 8-bit signed displacement */
119 SD16, /* 16-bit signed displacement */
120 SD24, /* 24-bit signed displacement */
121 SIMM4_2, /* 4-bit signed displacement in opcode bits 4-7 */
122 SIMM8, /* 8-bit signed immediate */
123 IMM24, /* 24-bit unsigned immediate */
124 IMM32, /* 32-bit unsigned immediate */
125 IMM32_HIGH8, /* 32-bit unsigned immediate, high 8-bits in opcode */
143 struct mn10300_opcode {
149 enum format_id format;
155 #define MEM(ADDR) (0x80000000 | (ADDR))
156 #define MEM2(ADDR1, ADDR2) (0x80000000 | (ADDR1) << 8 | (ADDR2))
157 #define MEMINC(ADDR) (0x81000000 | (ADDR))
158 #define MEMINC2(ADDR, INC) (0x81000000 | (ADDR) << 8 | (INC))
161 /* LIBOPCODES EXCERPT
162 Assemble Matsushita MN10300 instructions.
163 Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
165 This program is free software; you can redistribute it and/or modify
166 it under the terms of the GNU General Public Licence as published by
167 the Free Software Foundation; either version 2 of the Licence, or
168 (at your option) any later version.
170 This program is distributed in the hope that it will be useful,
171 but WITHOUT ANY WARRANTY; without even the implied warranty of
172 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
173 GNU General Public Licence for more details.
175 You should have received a copy of the GNU General Public Licence
176 along with this program; if not, write to the Free Software
177 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
179 static const struct mn10300_opcode mn10300_opcodes[] = {
180 { "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}},
181 { "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}},
182 { "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}},
183 { "mov", 0xf010, 0xfff0, 0, FMT_D0, 0, {AM1, MEM(AN0)}},
184 { "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
185 { "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
186 { "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}},
187 { "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}},
188 { "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
189 { "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
190 { "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
191 { "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}},
192 { "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM33, {MEM2(SD8, AM0), SP}},
193 { "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}},
194 { "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
195 { "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
196 { "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
197 { "mov", 0xf97a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
198 { "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
199 { "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
200 { "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
201 { "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}},
202 { "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
203 { "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
204 { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
205 { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
206 { "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
207 { "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
208 { "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
209 { "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
210 { "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}},
211 { "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}},
212 { "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
213 { "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
214 { "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
215 { "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
216 { "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
217 { "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
218 { "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
219 { "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
221 { "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}},
222 { "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
223 { "movhu", 0xf480, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
224 { "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
225 { "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
226 { "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
227 { "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
228 { "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
229 { "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
230 { "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
231 { "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
232 { "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
233 { "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
234 { "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
235 { "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
236 { "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
237 { "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
238 { "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
239 { "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
240 { "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
241 { "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
242 { "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
243 { "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
244 { "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
245 { "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
246 { "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
247 { "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
248 { "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
249 { 0, 0, 0, 0, 0, 0, {0}},
253 * fix up misalignment problems where possible
255 asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code)
257 const struct exception_table_entry *fixup;
258 const struct mn10300_opcode *pop;
259 unsigned long *registers = (unsigned long *) regs;
260 unsigned long data, *store, *postinc;
263 uint32_t opcode, disp, noc, xo, xm;
268 kdebug("==>misalignment({pc=%lx})", regs->pc);
271 die("Misalignment trap in interrupt context", regs, code);
273 if (regs->epsw & EPSW_IE)
274 asm volatile("or %0,epsw" : : "i"(EPSW_IE));
279 fixup = search_exception_tables(regs->pc);
281 /* first thing to do is to match the opcode */
282 pc = (u_int8_t *) regs->pc;
284 if (__get_user(byte, pc) != 0)
289 for (pop = mn10300_opcodes; pop->name; pop++) {
290 npop = ilog2(pop->opcode | pop->opmask);
291 if (npop <= 0 || npop > 31)
293 npop = (npop + 8) & ~7;
297 if ((opcode & pop->opmask) == pop->opcode)
299 } else if (npop > noc) {
300 xo = pop->opcode >> (npop - noc);
301 xm = pop->opmask >> (npop - noc);
303 if ((opcode & xm) != xo)
306 /* we've got a partial match (an exact match on the
307 * first N bytes), so we need to get some more data */
309 if (__get_user(byte, pc) != 0)
311 opcode = opcode << 8 | byte;
315 /* there's already been a partial match as long as the
316 * complete match we're now considering, so this one
322 /* didn't manage to find a fixup */
323 if (!user_mode(regs))
324 printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n",
329 if (die_if_no_fixup("misalignment error", regs, code))
332 info.si_signo = SIGBUS;
334 info.si_code = BUS_ADRALN;
335 info.si_addr = (void *) regs->pc;
336 force_sig_info(SIGBUS, &info, current);
339 /* error reading opcodes */
341 if (!user_mode(regs))
343 "MISALIGN: %p: fault whilst reading instruction data\n",
348 if (!user_mode(regs))
350 "MISALIGN: %lx: unsupported addressing mode %x\n",
355 if (!user_mode(regs))
357 "MISALIGN: %lx: unsupported register mode %x\n",
361 unsupported_instruction:
362 if (!user_mode(regs))
364 "MISALIGN: %lx: unsupported instruction %x (%s)\n",
365 regs->pc, opcode, pop->name);
371 regs->pc = fixup->fixup;
374 if (die_if_no_fixup("misalignment fixup", regs, code))
377 info.si_signo = SIGSEGV;
380 info.si_addr = (void *) regs->pc;
381 force_sig_info(SIGSEGV, &info, current);
384 /* we matched the opcode */
386 kdebug("%lx: %x==%x { %x, %x }",
387 regs->pc, opcode, pop->opcode, pop->params[0], pop->params[1]);
389 tmp = format_tbl[pop->format].opsz;
391 BUG(); /* match was less complete than it ought to have been */
399 /* grab the extra displacement (note it's LSB first) */
401 tmp = format_tbl[pop->format].dispsz >> 3;
407 if (__get_user(byte, pc) != 0)
413 if (fixup || regs->epsw & EPSW_nSL)
416 tmp = (pop->params[0] ^ pop->params[1]) & 0x80000000;
418 if (!user_mode(regs))
421 " insn not move to/from memory %x\n",
426 if (pop->params[0] & 0x80000000) {
427 /* move memory to register */
428 if (!misalignment_addr(registers, pop->params[0], opcode, disp,
432 if (!misalignment_reg(registers, pop->params[1], opcode, disp,
436 if (strcmp(pop->name, "mov") == 0) {
437 kdebug("mov (%p),DARn", address);
438 if (copy_from_user(&data, (void *) address, 4) != 0)
439 goto transfer_failed;
440 if (pop->params[0] & 0x1000000)
442 } else if (strcmp(pop->name, "movhu") == 0) {
443 kdebug("movhu (%p),DARn", address);
445 if (copy_from_user(&data, (void *) address, 2) != 0)
446 goto transfer_failed;
447 if (pop->params[0] & 0x1000000)
450 goto unsupported_instruction;
455 /* move register to memory */
456 if (!misalignment_reg(registers, pop->params[0], opcode, disp,
460 if (!misalignment_addr(registers, pop->params[1], opcode, disp,
466 if (strcmp(pop->name, "mov") == 0) {
467 kdebug("mov %lx,(%p)", data, address);
468 if (copy_to_user((void *) address, &data, 4) != 0)
469 goto transfer_failed;
470 if (pop->params[1] & 0x1000000)
472 } else if (strcmp(pop->name, "movhu") == 0) {
473 kdebug("movhu %hx,(%p)", (uint16_t) data, address);
474 if (copy_to_user((void *) address, &data, 2) != 0)
475 goto transfer_failed;
476 if (pop->params[1] & 0x1000000)
479 goto unsupported_instruction;
483 tmp = format_tbl[pop->format].opsz + format_tbl[pop->format].dispsz;
484 regs->pc += tmp >> 3;
491 * determine the address that was being accessed
493 static int misalignment_addr(unsigned long *registers, unsigned params,
494 unsigned opcode, unsigned disp,
495 void **_address, unsigned long **_postinc)
497 unsigned long *postinc = NULL, address = 0, tmp;
499 params &= 0x7fffffff;
502 switch (params & 0xff) {
504 postinc = ®isters[Dreg_index[opcode & 0x03]];
508 postinc = ®isters[Dreg_index[opcode >> 2 & 0x0c]];
512 postinc = ®isters[Dreg_index[opcode >> 4 & 0x30]];
516 postinc = ®isters[Areg_index[opcode & 0x03]];
520 postinc = ®isters[Areg_index[opcode >> 2 & 0x0c]];
524 postinc = ®isters[Areg_index[opcode >> 4 & 0x30]];
528 postinc = ®isters[Rreg_index[opcode & 0x0f]];
532 postinc = ®isters[Rreg_index[opcode >> 2 & 0x0f]];
536 postinc = ®isters[Rreg_index[opcode >> 4 & 0x0f]];
540 postinc = ®isters[Rreg_index[opcode >> 8 & 0x0f]];
544 postinc = ®isters[Rreg_index[opcode >> 12 & 0x0f]];
548 postinc = ®isters[Rreg_index[disp & 0x0f]];
552 postinc = ®isters[Rreg_index[disp >> 4 & 0x0f]];
558 address += (int32_t) (int8_t) (disp & 0xff);
561 address += (int32_t) (int16_t) (disp & 0xffff);
565 asm("asr 8,%0" : "=r"(tmp) : "0"(tmp));
569 tmp = opcode >> 4 & 0x0f;
571 asm("asr 28,%0" : "=r"(tmp) : "0"(tmp));
575 address += disp & 0x00ffffff;
584 } while ((params >>= 8));
586 *_address = (void *) address;
592 * determine the register that is acting as source/dest
594 static int misalignment_reg(unsigned long *registers, unsigned params,
595 unsigned opcode, unsigned disp,
596 unsigned long **_register)
598 params &= 0x7fffffff;
600 if (params & 0xffffff00)
603 switch (params & 0xff) {
605 *_register = ®isters[Dreg_index[opcode & 0x03]];
608 *_register = ®isters[Dreg_index[opcode >> 2 & 0x03]];
611 *_register = ®isters[Dreg_index[opcode >> 4 & 0x03]];
614 *_register = ®isters[Areg_index[opcode & 0x03]];
617 *_register = ®isters[Areg_index[opcode >> 2 & 0x03]];
620 *_register = ®isters[Areg_index[opcode >> 4 & 0x03]];
623 *_register = ®isters[Rreg_index[opcode & 0x0f]];
626 *_register = ®isters[Rreg_index[opcode >> 2 & 0x0f]];
629 *_register = ®isters[Rreg_index[opcode >> 4 & 0x0f]];
632 *_register = ®isters[Rreg_index[opcode >> 8 & 0x0f]];
635 *_register = ®isters[Rreg_index[opcode >> 12 & 0x0f]];
638 *_register = ®isters[Rreg_index[disp & 0x0f]];
641 *_register = ®isters[Rreg_index[disp >> 4 & 0x0f]];
644 *_register = ®isters[REG_SP >> 2];