2 * Setup pointers to hardware-dependent routines.
3 * Copyright (C) 2000-2001 Toshiba Corporation
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17 #include <linux/console.h>
18 #include <linux/platform_device.h>
19 #include <linux/gpio.h>
21 #include <asm/reboot.h>
23 #include <asm/txx9/generic.h>
24 #include <asm/txx9/pci.h>
25 #include <asm/txx9/rbtx4938.h>
26 #include <linux/spi/spi.h>
27 #include <asm/txx9/spi.h>
28 #include <asm/txx9pio.h>
30 static void rbtx4938_machine_restart(char *command)
33 writeb(1, rbtx4938_softresetlock_addr);
34 writeb(1, rbtx4938_sfvol_addr);
35 writeb(1, rbtx4938_softreset_addr);
40 static void __init rbtx4938_pci_setup(void)
43 int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
44 struct pci_controller *c = &txx9_primary_pcic;
46 register_pci_controller(c);
48 if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
50 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
51 TXX9_PCI_OPT_CLK_66; /* already configured */
54 writeb(0, rbtx4938_pcireset_addr);
56 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
57 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
59 tx4938_pciclk66_setup();
61 /* clear PCIC reset */
62 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
63 writeb(1, rbtx4938_pcireset_addr);
66 tx4938_report_pciclk();
67 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
68 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
69 TXX9_PCI_OPT_CLK_AUTO &&
70 txx9_pci66_check(c, 0, 0)) {
72 writeb(0, rbtx4938_pcireset_addr);
74 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
75 tx4938_pciclk66_setup();
77 /* clear PCIC reset */
78 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
79 writeb(1, rbtx4938_pcireset_addr);
81 /* Reinitialize PCIC */
82 tx4938_report_pciclk();
83 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
86 if (__raw_readq(&tx4938_ccfgptr->pcfg) &
87 (TX4938_PCFG_ETH0_SEL|TX4938_PCFG_ETH1_SEL)) {
89 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
90 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
91 if (!(__raw_readq(&tx4938_ccfgptr->ccfg)
92 & TX4938_CCFG_PCI1DMD))
93 tx4938_ccfg_set(TX4938_CCFG_PCI1_66);
95 /* clear PCIC1 reset */
96 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
97 tx4938_report_pci1clk();
99 /* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
100 c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
101 register_pci_controller(c);
102 tx4927_pcic_setup(tx4938_pcic1ptr, c, 0);
104 tx4938_setup_pcierr_irq();
105 #endif /* CONFIG_PCI */
110 /* chip select for SPI devices */
111 #define SEEPROM1_CS 7 /* PIO7 */
112 #define SEEPROM2_CS 0 /* IOC */
113 #define SEEPROM3_CS 1 /* IOC */
114 #define SRTC_CS 2 /* IOC */
116 static int __init rbtx4938_ethaddr_init(void)
119 unsigned char dat[17];
123 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
124 if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) {
125 printk(KERN_ERR "seeprom: read error.\n");
128 if (strcmp(dat, "MAC") != 0)
129 printk(KERN_WARNING "seeprom: bad signature.\n");
130 for (i = 0, sum = 0; i < sizeof(dat); i++)
133 printk(KERN_WARNING "seeprom: bad checksum.\n");
135 for (i = 0; i < 2; i++) {
137 TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0);
138 struct platform_device *pdev;
139 if (!(__raw_readq(&tx4938_ccfgptr->pcfg) &
140 (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL)))
142 pdev = platform_device_alloc("tc35815-mac", id);
144 platform_device_add_data(pdev, &dat[4 + 6 * i], 6) ||
145 platform_device_add(pdev))
146 platform_device_put(pdev);
148 #endif /* CONFIG_PCI */
152 static void __init rbtx4938_spi_setup(void)
155 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_SPI_SEL);
158 static struct resource rbtx4938_fpga_resource;
160 static void __init rbtx4938_time_init(void)
165 static void __init rbtx4938_mem_setup(void)
167 unsigned long long pcfg;
170 if (txx9_master_clock == 0)
171 txx9_master_clock = 25000000; /* 25MHz */
176 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
177 txx9_board_pcibios_setup = tx4927_pcibios_setup;
179 set_io_port_base(RBTX4938_ETHER_BASE);
182 tx4938_setup_serial();
183 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
184 argptr = prom_getcmdline();
185 if (strstr(argptr, "console=") == NULL) {
186 strcat(argptr, " console=ttyS0,38400");
190 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
191 printk("PIOSEL: disabling both ata and nand selection\n");
193 txx9_clear64(&tx4938_ccfgptr->pcfg,
194 TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
197 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
198 printk("PIOSEL: enabling nand selection\n");
199 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
200 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
203 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
204 printk("PIOSEL: enabling ata selection\n");
205 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
206 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
210 argptr = prom_getcmdline();
211 if (strstr(argptr, "ip=") == NULL) {
212 strcat(argptr, " ip=any");
219 conswitchp = &dummy_con;
223 rbtx4938_spi_setup();
224 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */
226 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
228 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04,
229 rbtx4938_piosel_addr);
230 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
232 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08,
233 rbtx4938_piosel_addr);
235 writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04),
236 rbtx4938_piosel_addr);
238 rbtx4938_fpga_resource.name = "FPGA Registers";
239 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
240 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
241 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
242 if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource))
243 printk("request resource for fpga failed\n");
245 _machine_restart = rbtx4938_machine_restart;
247 writeb(0xff, rbtx4938_led_addr);
248 printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
249 readb(rbtx4938_fpga_rev_addr),
250 readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
253 static int __init rbtx4938_ne_init(void)
255 struct resource res[] = {
257 .start = RBTX4938_RTL_8019_BASE,
258 .end = RBTX4938_RTL_8019_BASE + 0x20 - 1,
259 .flags = IORESOURCE_IO,
261 .start = RBTX4938_RTL_8019_IRQ,
262 .flags = IORESOURCE_IRQ,
265 struct platform_device *dev =
266 platform_device_register_simple("ne", -1,
267 res, ARRAY_SIZE(res));
268 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
271 static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
273 static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
278 spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
279 val = readb(rbtx4938_spics_addr);
283 val &= ~(1 << offset);
284 writeb(val, rbtx4938_spics_addr);
286 spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
289 static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip,
290 unsigned int offset, int value)
292 rbtx4938_spi_gpio_set(chip, offset, value);
296 static struct gpio_chip rbtx4938_spi_gpio_chip = {
297 .set = rbtx4938_spi_gpio_set,
298 .direction_output = rbtx4938_spi_gpio_dir_out,
299 .label = "RBTX4938-SPICS",
306 static void __init txx9_spi_init(unsigned long base, int irq)
308 struct resource res[] = {
311 .end = base + 0x20 - 1,
312 .flags = IORESOURCE_MEM,
315 .flags = IORESOURCE_IRQ,
318 platform_device_register_simple("spi_txx9", 0,
319 res, ARRAY_SIZE(res));
322 static int __init rbtx4938_spi_init(void)
324 struct spi_board_info srtc_info = {
325 .modalias = "rtc-rs5c348",
326 .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
328 .chip_select = 16 + SRTC_CS,
329 /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */
330 .mode = SPI_MODE_1 | SPI_CS_HIGH,
332 spi_register_board_info(&srtc_info, 1);
333 spi_eeprom_register(SEEPROM1_CS);
334 spi_eeprom_register(16 + SEEPROM2_CS);
335 spi_eeprom_register(16 + SEEPROM3_CS);
336 gpio_request(16 + SRTC_CS, "rtc-rs5c348");
337 gpio_direction_output(16 + SRTC_CS, 0);
338 gpio_request(SEEPROM1_CS, "seeprom1");
339 gpio_direction_output(SEEPROM1_CS, 1);
340 gpio_request(16 + SEEPROM2_CS, "seeprom2");
341 gpio_direction_output(16 + SEEPROM2_CS, 1);
342 gpio_request(16 + SEEPROM3_CS, "seeprom3");
343 gpio_direction_output(16 + SEEPROM3_CS, 1);
344 txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI);
348 static void __init rbtx4938_arch_init(void)
350 gpiochip_add(&rbtx4938_spi_gpio_chip);
351 rbtx4938_pci_setup();
355 static void __init rbtx4938_device_init(void)
357 rbtx4938_ethaddr_init();
362 struct txx9_board_vec rbtx4938_vec __initdata = {
363 .system = "Toshiba RBTX4938",
364 .prom_init = rbtx4938_prom_init,
365 .mem_setup = rbtx4938_mem_setup,
366 .irq_setup = rbtx4938_irq_setup,
367 .time_init = rbtx4938_time_init,
368 .device_init = rbtx4938_device_init,
369 .arch_init = rbtx4938_arch_init,
371 .pci_map_irq = rbtx4938_pci_map_irq,