2 * Setup pointers to hardware-dependent routines.
3 * Copyright (C) 2000-2001 Toshiba Corporation
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/delay.h>
16 #include <linux/platform_device.h>
17 #include <linux/gpio.h>
18 #include <linux/mtd/physmap.h>
20 #include <asm/reboot.h>
22 #include <asm/txx9/generic.h>
23 #include <asm/txx9/pci.h>
24 #include <asm/txx9/rbtx4938.h>
25 #include <linux/spi/spi.h>
26 #include <asm/txx9/spi.h>
27 #include <asm/txx9pio.h>
29 static void rbtx4938_machine_restart(char *command)
32 writeb(1, rbtx4938_softresetlock_addr);
33 writeb(1, rbtx4938_sfvol_addr);
34 writeb(1, rbtx4938_softreset_addr);
39 static void __init rbtx4938_pci_setup(void)
42 int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
43 struct pci_controller *c = &txx9_primary_pcic;
45 register_pci_controller(c);
47 if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
49 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
50 TXX9_PCI_OPT_CLK_66; /* already configured */
53 writeb(0, rbtx4938_pcireset_addr);
55 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
56 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
58 tx4938_pciclk66_setup();
60 /* clear PCIC reset */
61 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
62 writeb(1, rbtx4938_pcireset_addr);
65 tx4938_report_pciclk();
66 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
67 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
68 TXX9_PCI_OPT_CLK_AUTO &&
69 txx9_pci66_check(c, 0, 0)) {
71 writeb(0, rbtx4938_pcireset_addr);
73 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
74 tx4938_pciclk66_setup();
76 /* clear PCIC reset */
77 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
78 writeb(1, rbtx4938_pcireset_addr);
80 /* Reinitialize PCIC */
81 tx4938_report_pciclk();
82 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
85 if (__raw_readq(&tx4938_ccfgptr->pcfg) &
86 (TX4938_PCFG_ETH0_SEL|TX4938_PCFG_ETH1_SEL)) {
88 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
89 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
90 if (!(__raw_readq(&tx4938_ccfgptr->ccfg)
91 & TX4938_CCFG_PCI1DMD))
92 tx4938_ccfg_set(TX4938_CCFG_PCI1_66);
94 /* clear PCIC1 reset */
95 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
96 tx4938_report_pci1clk();
98 /* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
99 c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
100 register_pci_controller(c);
101 tx4927_pcic_setup(tx4938_pcic1ptr, c, 0);
103 tx4938_setup_pcierr_irq();
104 #endif /* CONFIG_PCI */
109 /* chip select for SPI devices */
110 #define SEEPROM1_CS 7 /* PIO7 */
111 #define SEEPROM2_CS 0 /* IOC */
112 #define SEEPROM3_CS 1 /* IOC */
113 #define SRTC_CS 2 /* IOC */
115 static int __init rbtx4938_ethaddr_init(void)
118 unsigned char dat[17];
122 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
123 if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) {
124 printk(KERN_ERR "seeprom: read error.\n");
127 if (strcmp(dat, "MAC") != 0)
128 printk(KERN_WARNING "seeprom: bad signature.\n");
129 for (i = 0, sum = 0; i < sizeof(dat); i++)
132 printk(KERN_WARNING "seeprom: bad checksum.\n");
134 tx4938_ethaddr_init(&dat[4], &dat[4 + 6]);
135 #endif /* CONFIG_PCI */
139 static void __init rbtx4938_spi_setup(void)
142 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_SPI_SEL);
145 static struct resource rbtx4938_fpga_resource;
147 static void __init rbtx4938_time_init(void)
152 static void __init rbtx4938_mem_setup(void)
154 unsigned long long pcfg;
157 if (txx9_master_clock == 0)
158 txx9_master_clock = 25000000; /* 25MHz */
163 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
164 txx9_board_pcibios_setup = tx4927_pcibios_setup;
166 set_io_port_base(RBTX4938_ETHER_BASE);
169 tx4938_sio_init(7372800, 0);
170 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
171 argptr = prom_getcmdline();
172 if (!strstr(argptr, "console="))
173 strcat(argptr, " console=ttyS0,38400");
176 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
177 pr_info("PIOSEL: disabling both ATA and NAND selection\n");
178 txx9_clear64(&tx4938_ccfgptr->pcfg,
179 TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
182 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
183 pr_info("PIOSEL: enabling NAND selection\n");
184 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
185 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
188 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
189 pr_info("PIOSEL: enabling ATA selection\n");
190 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
191 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
194 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_KEEP
195 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
196 pr_info("PIOSEL: NAND %s, ATA %s\n",
197 (pcfg & TX4938_PCFG_NDF_SEL) ? "enabled" : "disabled",
198 (pcfg & TX4938_PCFG_ATA_SEL) ? "enabled" : "disabled");
201 rbtx4938_spi_setup();
202 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */
204 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
206 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04,
207 rbtx4938_piosel_addr);
208 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
210 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08,
211 rbtx4938_piosel_addr);
213 writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04),
214 rbtx4938_piosel_addr);
216 rbtx4938_fpga_resource.name = "FPGA Registers";
217 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
218 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
219 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
220 if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource))
221 printk(KERN_ERR "request resource for fpga failed\n");
223 _machine_restart = rbtx4938_machine_restart;
225 writeb(0xff, rbtx4938_led_addr);
226 printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
227 readb(rbtx4938_fpga_rev_addr),
228 readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
231 static void __init rbtx4938_ne_init(void)
233 struct resource res[] = {
235 .start = RBTX4938_RTL_8019_BASE,
236 .end = RBTX4938_RTL_8019_BASE + 0x20 - 1,
237 .flags = IORESOURCE_IO,
239 .start = RBTX4938_RTL_8019_IRQ,
240 .flags = IORESOURCE_IRQ,
243 platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
246 static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
248 static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
253 spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
254 val = readb(rbtx4938_spics_addr);
258 val &= ~(1 << offset);
259 writeb(val, rbtx4938_spics_addr);
261 spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
264 static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip,
265 unsigned int offset, int value)
267 rbtx4938_spi_gpio_set(chip, offset, value);
271 static struct gpio_chip rbtx4938_spi_gpio_chip = {
272 .set = rbtx4938_spi_gpio_set,
273 .direction_output = rbtx4938_spi_gpio_dir_out,
274 .label = "RBTX4938-SPICS",
279 static int __init rbtx4938_spi_init(void)
281 struct spi_board_info srtc_info = {
282 .modalias = "rtc-rs5c348",
283 .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
285 .chip_select = 16 + SRTC_CS,
286 /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */
287 .mode = SPI_MODE_1 | SPI_CS_HIGH,
289 spi_register_board_info(&srtc_info, 1);
290 spi_eeprom_register(SEEPROM1_CS);
291 spi_eeprom_register(16 + SEEPROM2_CS);
292 spi_eeprom_register(16 + SEEPROM3_CS);
293 gpio_request(16 + SRTC_CS, "rtc-rs5c348");
294 gpio_direction_output(16 + SRTC_CS, 0);
295 gpio_request(SEEPROM1_CS, "seeprom1");
296 gpio_direction_output(SEEPROM1_CS, 1);
297 gpio_request(16 + SEEPROM2_CS, "seeprom2");
298 gpio_direction_output(16 + SEEPROM2_CS, 1);
299 gpio_request(16 + SEEPROM3_CS, "seeprom3");
300 gpio_direction_output(16 + SEEPROM3_CS, 1);
305 static void __init rbtx4938_mtd_init(void)
307 struct physmap_flash_data pdata = {
311 switch (readb(rbtx4938_bdipsw_addr) & 7) {
314 txx9_physmap_flash_init(0, 0x1fc00000, 0x400000, &pdata);
316 txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
320 txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
322 txx9_physmap_flash_init(1, 0x1ec00000, 0x400000, &pdata);
326 txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
328 txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
330 txx9_physmap_flash_init(2, 0x1dc00000, 0x400000, &pdata);
334 txx9_physmap_flash_init(1, 0x1bc00000, 0x400000, &pdata);
336 txx9_physmap_flash_init(2, 0x1a000000, 0x1000000, &pdata);
341 static void __init rbtx4938_arch_init(void)
343 gpiochip_add(&rbtx4938_spi_gpio_chip);
344 rbtx4938_pci_setup();
348 static void __init rbtx4938_device_init(void)
350 rbtx4938_ethaddr_init();
356 struct txx9_board_vec rbtx4938_vec __initdata = {
357 .system = "Toshiba RBTX4938",
358 .prom_init = rbtx4938_prom_init,
359 .mem_setup = rbtx4938_mem_setup,
360 .irq_setup = rbtx4938_irq_setup,
361 .time_init = rbtx4938_time_init,
362 .device_init = rbtx4938_device_init,
363 .arch_init = rbtx4938_arch_init,
365 .pci_map_irq = rbtx4938_pci_map_irq,