2 * Setup pointers to hardware-dependent routines.
3 * Copyright (C) 2000-2001 Toshiba Corporation
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17 #include <linux/console.h>
19 #include <linux/platform_device.h>
20 #include <linux/gpio.h>
22 #include <asm/reboot.h>
24 #include <asm/txx9tmr.h>
26 #include <asm/bootinfo.h>
27 #include <asm/txx9/generic.h>
28 #include <asm/txx9/pci.h>
29 #include <asm/txx9/rbtx4938.h>
30 #ifdef CONFIG_SERIAL_TXX9
31 #include <linux/serial_core.h>
33 #include <linux/spi/spi.h>
34 #include <asm/txx9/spi.h>
35 #include <asm/txx9pio.h>
37 extern char * __init prom_getcmdline(void);
38 /* These functions are used for rebooting or halting the machine*/
39 extern void rbtx4938_machine_restart(char *command);
40 extern void rbtx4938_machine_halt(void);
41 extern void rbtx4938_machine_power_off(void);
43 static int tx4938_ccfg_toeon = 1;
45 void rbtx4938_machine_halt(void)
47 printk(KERN_NOTICE "System Halted\n");
51 __asm__(".set\tmips3\n\t"
56 void rbtx4938_machine_power_off(void)
58 rbtx4938_machine_halt();
62 void rbtx4938_machine_restart(char *command)
66 printk("Rebooting...");
67 writeb(1, rbtx4938_softresetlock_addr);
68 writeb(1, rbtx4938_sfvol_addr);
69 writeb(1, rbtx4938_softreset_addr);
74 static void __init rbtx4938_pci_setup(void)
77 int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
78 struct pci_controller *c = &txx9_primary_pcic;
80 register_pci_controller(c);
82 if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
84 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
85 TXX9_PCI_OPT_CLK_66; /* already configured */
88 writeb(0, rbtx4938_pcireset_addr);
90 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
91 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
93 tx4938_pciclk66_setup();
95 /* clear PCIC reset */
96 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
97 writeb(1, rbtx4938_pcireset_addr);
100 tx4938_report_pciclk();
101 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
102 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
103 TXX9_PCI_OPT_CLK_AUTO &&
104 txx9_pci66_check(c, 0, 0)) {
106 writeb(0, rbtx4938_pcireset_addr);
108 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
109 tx4938_pciclk66_setup();
111 /* clear PCIC reset */
112 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
113 writeb(1, rbtx4938_pcireset_addr);
115 /* Reinitialize PCIC */
116 tx4938_report_pciclk();
117 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
120 if (__raw_readq(&tx4938_ccfgptr->pcfg) &
121 (TX4938_PCFG_ETH0_SEL|TX4938_PCFG_ETH1_SEL)) {
123 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
124 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
125 if (!(__raw_readq(&tx4938_ccfgptr->ccfg)
126 & TX4938_CCFG_PCI1DMD))
127 tx4938_ccfg_set(TX4938_CCFG_PCI1_66);
129 /* clear PCIC1 reset */
130 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
131 tx4938_report_pci1clk();
133 /* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
134 c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
135 register_pci_controller(c);
136 tx4927_pcic_setup(tx4938_pcic1ptr, c, 0);
138 #endif /* CONFIG_PCI */
143 /* chip select for SPI devices */
144 #define SEEPROM1_CS 7 /* PIO7 */
145 #define SEEPROM2_CS 0 /* IOC */
146 #define SEEPROM3_CS 1 /* IOC */
147 #define SRTC_CS 2 /* IOC */
149 static int __init rbtx4938_ethaddr_init(void)
152 unsigned char dat[17];
156 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
157 if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) {
158 printk(KERN_ERR "seeprom: read error.\n");
161 if (strcmp(dat, "MAC") != 0)
162 printk(KERN_WARNING "seeprom: bad signature.\n");
163 for (i = 0, sum = 0; i < sizeof(dat); i++)
166 printk(KERN_WARNING "seeprom: bad checksum.\n");
168 for (i = 0; i < 2; i++) {
170 TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0);
171 struct platform_device *pdev;
172 if (!(__raw_readq(&tx4938_ccfgptr->pcfg) &
173 (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL)))
175 pdev = platform_device_alloc("tc35815-mac", id);
177 platform_device_add_data(pdev, &dat[4 + 6 * i], 6) ||
178 platform_device_add(pdev))
179 platform_device_put(pdev);
181 #endif /* CONFIG_PCI */
185 static void __init rbtx4938_spi_setup(void)
188 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_SPI_SEL);
191 static struct resource rbtx4938_fpga_resource;
192 static struct resource tx4938_sdram_resource[4];
193 static struct resource tx4938_sram_resource;
195 void __init tx4938_board_setup(void)
198 unsigned long divmode;
200 unsigned long pcode = TX4938_REV_PCODE();
202 ioport_resource.start = 0;
203 ioport_resource.end = 0xffffffff;
204 iomem_resource.start = 0;
205 iomem_resource.end = 0xffffffff; /* expand to 4GB */
207 txx9_reg_res_init(pcode, TX4938_REG_BASE,
209 /* SDRAMC,EBUSC are configured by PROM */
210 for (i = 0; i < 8; i++) {
211 if (!(TX4938_EBUSC_CR(i) & 0x8))
212 continue; /* disabled */
213 txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i);
215 txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1;
216 request_resource(&iomem_resource, &txx9_ce_res[i]);
220 if (txx9_master_clock) {
221 u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
222 /* calculate gbus_clock and cpu_clock_freq from master_clock */
223 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
225 case TX4938_CCFG_DIVMODE_8:
226 case TX4938_CCFG_DIVMODE_10:
227 case TX4938_CCFG_DIVMODE_12:
228 case TX4938_CCFG_DIVMODE_16:
229 case TX4938_CCFG_DIVMODE_18:
230 txx9_gbus_clock = txx9_master_clock * 4; break;
232 txx9_gbus_clock = txx9_master_clock;
235 case TX4938_CCFG_DIVMODE_2:
236 case TX4938_CCFG_DIVMODE_8:
237 cpuclk = txx9_gbus_clock * 2; break;
238 case TX4938_CCFG_DIVMODE_2_5:
239 case TX4938_CCFG_DIVMODE_10:
240 cpuclk = txx9_gbus_clock * 5 / 2; break;
241 case TX4938_CCFG_DIVMODE_3:
242 case TX4938_CCFG_DIVMODE_12:
243 cpuclk = txx9_gbus_clock * 3; break;
244 case TX4938_CCFG_DIVMODE_4:
245 case TX4938_CCFG_DIVMODE_16:
246 cpuclk = txx9_gbus_clock * 4; break;
247 case TX4938_CCFG_DIVMODE_4_5:
248 case TX4938_CCFG_DIVMODE_18:
249 cpuclk = txx9_gbus_clock * 9 / 2; break;
251 txx9_cpu_clock = cpuclk;
253 u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
254 if (txx9_cpu_clock == 0) {
255 txx9_cpu_clock = 300000000; /* 300MHz */
257 /* calculate gbus_clock and master_clock from cpu_clock_freq */
258 cpuclk = txx9_cpu_clock;
259 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
261 case TX4938_CCFG_DIVMODE_2:
262 case TX4938_CCFG_DIVMODE_8:
263 txx9_gbus_clock = cpuclk / 2; break;
264 case TX4938_CCFG_DIVMODE_2_5:
265 case TX4938_CCFG_DIVMODE_10:
266 txx9_gbus_clock = cpuclk * 2 / 5; break;
267 case TX4938_CCFG_DIVMODE_3:
268 case TX4938_CCFG_DIVMODE_12:
269 txx9_gbus_clock = cpuclk / 3; break;
270 case TX4938_CCFG_DIVMODE_4:
271 case TX4938_CCFG_DIVMODE_16:
272 txx9_gbus_clock = cpuclk / 4; break;
273 case TX4938_CCFG_DIVMODE_4_5:
274 case TX4938_CCFG_DIVMODE_18:
275 txx9_gbus_clock = cpuclk * 2 / 9; break;
278 case TX4938_CCFG_DIVMODE_8:
279 case TX4938_CCFG_DIVMODE_10:
280 case TX4938_CCFG_DIVMODE_12:
281 case TX4938_CCFG_DIVMODE_16:
282 case TX4938_CCFG_DIVMODE_18:
283 txx9_master_clock = txx9_gbus_clock / 4; break;
285 txx9_master_clock = txx9_gbus_clock;
288 /* change default value to udelay/mdelay take reasonable time */
289 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
292 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
293 tx4938_ccfg_set(TX4938_CCFG_WDRST | TX4938_CCFG_BEOW);
294 /* do reset on watchdog */
295 tx4938_ccfg_set(TX4938_CCFG_WR);
296 /* clear PCIC1 reset */
297 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
299 /* enable Timeout BusError */
300 if (tx4938_ccfg_toeon)
301 tx4938_ccfg_set(TX4938_CCFG_TOE);
304 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL);
306 /* Use external clock for external arbiter */
307 if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
308 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
310 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
312 (cpuclk + 500000) / 1000000,
313 (txx9_master_clock + 500000) / 1000000,
314 (__u32)____raw_readq(&tx4938_ccfgptr->crir),
315 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
316 (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
318 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
319 for (i = 0; i < 4; i++) {
320 unsigned long long cr = tx4938_sdramcptr->cr[i];
321 unsigned long ram_base, ram_size;
322 if (!((unsigned long)cr & 0x00000400))
323 continue; /* disabled */
324 ram_base = (unsigned long)(cr >> 49) << 21;
325 ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
326 if (ram_base >= 0x20000000)
327 continue; /* high memory (ignore) */
328 printk(" CR%d:%016Lx", i, cr);
329 tx4938_sdram_resource[i].name = "SDRAM";
330 tx4938_sdram_resource[i].start = ram_base;
331 tx4938_sdram_resource[i].end = ram_base + ram_size - 1;
332 tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
333 request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
335 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr);
338 if (tx4938_sramcptr->cr & 1) {
339 unsigned int size = 0x800;
341 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1);
342 tx4938_sram_resource.name = "SRAM";
343 tx4938_sram_resource.start = base;
344 tx4938_sram_resource.end = base + size - 1;
345 tx4938_sram_resource.flags = IORESOURCE_MEM;
346 request_resource(&iomem_resource, &tx4938_sram_resource);
350 for (i = 0; i < TX4938_NR_TMR; i++)
351 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
354 for (i = 0; i < 2; i++)
355 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
356 (void __iomem *)(TX4938_DMA_REG(i) + 0x50));
359 __raw_writel(0, &tx4938_pioptr->maskcpu);
360 __raw_writel(0, &tx4938_pioptr->maskext);
363 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
367 static void __init rbtx4938_time_init(void)
369 mips_hpt_frequency = txx9_cpu_clock / 2;
370 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS)
371 txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL,
372 TXX9_IRQ_BASE + TX4938_IR_TMR(0),
373 txx9_gbus_clock / 2);
376 static void __init rbtx4938_mem_setup(void)
378 unsigned long long pcfg;
381 iomem_resource.end = 0xffffffff; /* 4GB */
383 if (txx9_master_clock == 0)
384 txx9_master_clock = 25000000; /* 25MHz */
385 tx4938_board_setup();
387 set_io_port_base(RBTX4938_ETHER_BASE);
390 #ifdef CONFIG_SERIAL_TXX9
392 extern int early_serial_txx9_setup(struct uart_port *port);
394 struct uart_port req;
395 for(i = 0; i < 2; i++) {
396 memset(&req, 0, sizeof(req));
398 req.iotype = UPIO_MEM;
399 req.membase = (char *)(0xff1ff300 + i * 0x100);
400 req.mapbase = 0xff1ff300 + i * 0x100;
401 req.irq = RBTX4938_IRQ_IRC_SIO(i);
402 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
403 req.uartclk = 50000000;
404 early_serial_txx9_setup(&req);
407 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
408 argptr = prom_getcmdline();
409 if (strstr(argptr, "console=") == NULL) {
410 strcat(argptr, " console=ttyS0,38400");
415 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
416 printk("PIOSEL: disabling both ata and nand selection\n");
418 txx9_clear64(&tx4938_ccfgptr->pcfg,
419 TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
422 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
423 printk("PIOSEL: enabling nand selection\n");
424 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
425 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
428 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
429 printk("PIOSEL: enabling ata selection\n");
430 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
431 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
435 argptr = prom_getcmdline();
436 if (strstr(argptr, "ip=") == NULL) {
437 strcat(argptr, " ip=any");
444 conswitchp = &dummy_con;
448 rbtx4938_spi_setup();
449 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */
451 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
453 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04,
454 rbtx4938_piosel_addr);
455 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
457 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08,
458 rbtx4938_piosel_addr);
460 writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04),
461 rbtx4938_piosel_addr);
463 rbtx4938_fpga_resource.name = "FPGA Registers";
464 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
465 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
466 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
467 if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))
468 printk("request resource for fpga failed\n");
470 _machine_restart = rbtx4938_machine_restart;
471 _machine_halt = rbtx4938_machine_halt;
472 pm_power_off = rbtx4938_machine_power_off;
474 writeb(0xff, rbtx4938_led_addr);
475 printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
476 readb(rbtx4938_fpga_rev_addr),
477 readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
480 static int __init rbtx4938_ne_init(void)
482 struct resource res[] = {
484 .start = RBTX4938_RTL_8019_BASE,
485 .end = RBTX4938_RTL_8019_BASE + 0x20 - 1,
486 .flags = IORESOURCE_IO,
488 .start = RBTX4938_RTL_8019_IRQ,
489 .flags = IORESOURCE_IRQ,
492 struct platform_device *dev =
493 platform_device_register_simple("ne", -1,
494 res, ARRAY_SIZE(res));
495 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
500 int gpio_to_irq(unsigned gpio)
505 int irq_to_gpio(unsigned irq)
510 static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
512 static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
517 spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
518 val = readb(rbtx4938_spics_addr);
522 val &= ~(1 << offset);
523 writeb(val, rbtx4938_spics_addr);
525 spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
528 static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip,
529 unsigned int offset, int value)
531 rbtx4938_spi_gpio_set(chip, offset, value);
535 static struct gpio_chip rbtx4938_spi_gpio_chip = {
536 .set = rbtx4938_spi_gpio_set,
537 .direction_output = rbtx4938_spi_gpio_dir_out,
538 .label = "RBTX4938-SPICS",
545 static void __init txx9_spi_init(unsigned long base, int irq)
547 struct resource res[] = {
550 .end = base + 0x20 - 1,
551 .flags = IORESOURCE_MEM,
554 .flags = IORESOURCE_IRQ,
557 platform_device_register_simple("spi_txx9", 0,
558 res, ARRAY_SIZE(res));
561 static int __init rbtx4938_spi_init(void)
563 struct spi_board_info srtc_info = {
564 .modalias = "rtc-rs5c348",
565 .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
567 .chip_select = 16 + SRTC_CS,
568 /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */
569 .mode = SPI_MODE_1 | SPI_CS_HIGH,
571 spi_register_board_info(&srtc_info, 1);
572 spi_eeprom_register(SEEPROM1_CS);
573 spi_eeprom_register(16 + SEEPROM2_CS);
574 spi_eeprom_register(16 + SEEPROM3_CS);
575 gpio_request(16 + SRTC_CS, "rtc-rs5c348");
576 gpio_direction_output(16 + SRTC_CS, 0);
577 gpio_request(SEEPROM1_CS, "seeprom1");
578 gpio_direction_output(SEEPROM1_CS, 1);
579 gpio_request(16 + SEEPROM2_CS, "seeprom2");
580 gpio_direction_output(16 + SEEPROM2_CS, 1);
581 gpio_request(16 + SEEPROM3_CS, "seeprom3");
582 gpio_direction_output(16 + SEEPROM3_CS, 1);
583 txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI);
587 static void __init rbtx4938_arch_init(void)
589 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16);
590 gpiochip_add(&rbtx4938_spi_gpio_chip);
591 rbtx4938_pci_setup();
595 /* Watchdog support */
597 static int __init txx9_wdt_init(unsigned long base)
599 struct resource res = {
601 .end = base + 0x100 - 1,
602 .flags = IORESOURCE_MEM,
604 struct platform_device *dev =
605 platform_device_register_simple("txx9wdt", -1, &res, 1);
606 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
609 static int __init rbtx4938_wdt_init(void)
611 return txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL);
614 static void __init rbtx4938_device_init(void)
616 rbtx4938_ethaddr_init();
621 struct txx9_board_vec rbtx4938_vec __initdata = {
622 .system = "Toshiba RBTX4938",
623 .prom_init = rbtx4938_prom_init,
624 .mem_setup = rbtx4938_mem_setup,
625 .irq_setup = rbtx4938_irq_setup,
626 .time_init = rbtx4938_time_init,
627 .device_init = rbtx4938_device_init,
628 .arch_init = rbtx4938_arch_init,
630 .pci_map_irq = rbtx4938_pci_map_irq,