2 * Setup pointers to hardware-dependent routines.
3 * Copyright (C) 2000-2001 Toshiba Corporation
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17 #include <linux/console.h>
19 #include <linux/platform_device.h>
20 #include <linux/clk.h>
21 #include <linux/gpio.h>
23 #include <asm/reboot.h>
25 #include <asm/txx9tmr.h>
27 #include <asm/bootinfo.h>
28 #include <asm/txx9/generic.h>
29 #include <asm/txx9/pci.h>
30 #include <asm/txx9/rbtx4938.h>
31 #ifdef CONFIG_SERIAL_TXX9
32 #include <linux/serial_core.h>
34 #include <linux/spi/spi.h>
35 #include <asm/txx9/spi.h>
36 #include <asm/txx9pio.h>
38 extern char * __init prom_getcmdline(void);
39 /* These functions are used for rebooting or halting the machine*/
40 extern void rbtx4938_machine_restart(char *command);
41 extern void rbtx4938_machine_halt(void);
42 extern void rbtx4938_machine_power_off(void);
44 static int tx4938_ccfg_toeon = 1;
46 void rbtx4938_machine_halt(void)
48 printk(KERN_NOTICE "System Halted\n");
52 __asm__(".set\tmips3\n\t"
57 void rbtx4938_machine_power_off(void)
59 rbtx4938_machine_halt();
63 void rbtx4938_machine_restart(char *command)
67 printk("Rebooting...");
68 writeb(1, rbtx4938_softresetlock_addr);
69 writeb(1, rbtx4938_sfvol_addr);
70 writeb(1, rbtx4938_softreset_addr);
75 static void __init rbtx4938_pci_setup(void)
78 int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
79 struct pci_controller *c = &txx9_primary_pcic;
81 register_pci_controller(c);
83 if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
85 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
86 TXX9_PCI_OPT_CLK_66; /* already configured */
89 writeb(0, rbtx4938_pcireset_addr);
91 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
92 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
94 tx4938_pciclk66_setup();
96 /* clear PCIC reset */
97 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
98 writeb(1, rbtx4938_pcireset_addr);
101 tx4938_report_pciclk();
102 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
103 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
104 TXX9_PCI_OPT_CLK_AUTO &&
105 txx9_pci66_check(c, 0, 0)) {
107 writeb(0, rbtx4938_pcireset_addr);
109 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
110 tx4938_pciclk66_setup();
112 /* clear PCIC reset */
113 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
114 writeb(1, rbtx4938_pcireset_addr);
116 /* Reinitialize PCIC */
117 tx4938_report_pciclk();
118 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
121 if (__raw_readq(&tx4938_ccfgptr->pcfg) &
122 (TX4938_PCFG_ETH0_SEL|TX4938_PCFG_ETH1_SEL)) {
124 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
125 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
126 if (!(__raw_readq(&tx4938_ccfgptr->ccfg)
127 & TX4938_CCFG_PCI1DMD))
128 tx4938_ccfg_set(TX4938_CCFG_PCI1_66);
130 /* clear PCIC1 reset */
131 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
132 tx4938_report_pci1clk();
134 /* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
135 c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
136 register_pci_controller(c);
137 tx4927_pcic_setup(tx4938_pcic1ptr, c, 0);
139 #endif /* CONFIG_PCI */
144 /* chip select for SPI devices */
145 #define SEEPROM1_CS 7 /* PIO7 */
146 #define SEEPROM2_CS 0 /* IOC */
147 #define SEEPROM3_CS 1 /* IOC */
148 #define SRTC_CS 2 /* IOC */
151 static int __init rbtx4938_ethaddr_init(void)
153 unsigned char dat[17];
157 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
158 if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) {
159 printk(KERN_ERR "seeprom: read error.\n");
162 if (strcmp(dat, "MAC") != 0)
163 printk(KERN_WARNING "seeprom: bad signature.\n");
164 for (i = 0, sum = 0; i < sizeof(dat); i++)
167 printk(KERN_WARNING "seeprom: bad checksum.\n");
169 for (i = 0; i < 2; i++) {
171 TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0);
172 struct platform_device *pdev;
173 if (!(__raw_readq(&tx4938_ccfgptr->pcfg) &
174 (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL)))
176 pdev = platform_device_alloc("tc35815-mac", id);
178 platform_device_add_data(pdev, &dat[4 + 6 * i], 6) ||
179 platform_device_add(pdev))
180 platform_device_put(pdev);
184 device_initcall(rbtx4938_ethaddr_init);
185 #endif /* CONFIG_PCI */
187 static void __init rbtx4938_spi_setup(void)
190 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_SPI_SEL);
193 static struct resource rbtx4938_fpga_resource;
194 static struct resource tx4938_sdram_resource[4];
195 static struct resource tx4938_sram_resource;
197 void __init tx4938_board_setup(void)
200 unsigned long divmode;
202 unsigned long pcode = TX4938_REV_PCODE();
204 ioport_resource.start = 0;
205 ioport_resource.end = 0xffffffff;
206 iomem_resource.start = 0;
207 iomem_resource.end = 0xffffffff; /* expand to 4GB */
209 txx9_reg_res_init(pcode, TX4938_REG_BASE,
211 /* SDRAMC,EBUSC are configured by PROM */
212 for (i = 0; i < 8; i++) {
213 if (!(TX4938_EBUSC_CR(i) & 0x8))
214 continue; /* disabled */
215 txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i);
217 txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1;
218 request_resource(&iomem_resource, &txx9_ce_res[i]);
222 if (txx9_master_clock) {
223 u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
224 /* calculate gbus_clock and cpu_clock_freq from master_clock */
225 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
227 case TX4938_CCFG_DIVMODE_8:
228 case TX4938_CCFG_DIVMODE_10:
229 case TX4938_CCFG_DIVMODE_12:
230 case TX4938_CCFG_DIVMODE_16:
231 case TX4938_CCFG_DIVMODE_18:
232 txx9_gbus_clock = txx9_master_clock * 4; break;
234 txx9_gbus_clock = txx9_master_clock;
237 case TX4938_CCFG_DIVMODE_2:
238 case TX4938_CCFG_DIVMODE_8:
239 cpuclk = txx9_gbus_clock * 2; break;
240 case TX4938_CCFG_DIVMODE_2_5:
241 case TX4938_CCFG_DIVMODE_10:
242 cpuclk = txx9_gbus_clock * 5 / 2; break;
243 case TX4938_CCFG_DIVMODE_3:
244 case TX4938_CCFG_DIVMODE_12:
245 cpuclk = txx9_gbus_clock * 3; break;
246 case TX4938_CCFG_DIVMODE_4:
247 case TX4938_CCFG_DIVMODE_16:
248 cpuclk = txx9_gbus_clock * 4; break;
249 case TX4938_CCFG_DIVMODE_4_5:
250 case TX4938_CCFG_DIVMODE_18:
251 cpuclk = txx9_gbus_clock * 9 / 2; break;
253 txx9_cpu_clock = cpuclk;
255 u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
256 if (txx9_cpu_clock == 0) {
257 txx9_cpu_clock = 300000000; /* 300MHz */
259 /* calculate gbus_clock and master_clock from cpu_clock_freq */
260 cpuclk = txx9_cpu_clock;
261 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
263 case TX4938_CCFG_DIVMODE_2:
264 case TX4938_CCFG_DIVMODE_8:
265 txx9_gbus_clock = cpuclk / 2; break;
266 case TX4938_CCFG_DIVMODE_2_5:
267 case TX4938_CCFG_DIVMODE_10:
268 txx9_gbus_clock = cpuclk * 2 / 5; break;
269 case TX4938_CCFG_DIVMODE_3:
270 case TX4938_CCFG_DIVMODE_12:
271 txx9_gbus_clock = cpuclk / 3; break;
272 case TX4938_CCFG_DIVMODE_4:
273 case TX4938_CCFG_DIVMODE_16:
274 txx9_gbus_clock = cpuclk / 4; break;
275 case TX4938_CCFG_DIVMODE_4_5:
276 case TX4938_CCFG_DIVMODE_18:
277 txx9_gbus_clock = cpuclk * 2 / 9; break;
280 case TX4938_CCFG_DIVMODE_8:
281 case TX4938_CCFG_DIVMODE_10:
282 case TX4938_CCFG_DIVMODE_12:
283 case TX4938_CCFG_DIVMODE_16:
284 case TX4938_CCFG_DIVMODE_18:
285 txx9_master_clock = txx9_gbus_clock / 4; break;
287 txx9_master_clock = txx9_gbus_clock;
290 /* change default value to udelay/mdelay take reasonable time */
291 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
294 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
295 tx4938_ccfg_set(TX4938_CCFG_WDRST | TX4938_CCFG_BEOW);
296 /* do reset on watchdog */
297 tx4938_ccfg_set(TX4938_CCFG_WR);
298 /* clear PCIC1 reset */
299 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
301 /* enable Timeout BusError */
302 if (tx4938_ccfg_toeon)
303 tx4938_ccfg_set(TX4938_CCFG_TOE);
306 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL);
308 /* Use external clock for external arbiter */
309 if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
310 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
312 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
314 (cpuclk + 500000) / 1000000,
315 (txx9_master_clock + 500000) / 1000000,
316 (__u32)____raw_readq(&tx4938_ccfgptr->crir),
317 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
318 (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
320 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
321 for (i = 0; i < 4; i++) {
322 unsigned long long cr = tx4938_sdramcptr->cr[i];
323 unsigned long ram_base, ram_size;
324 if (!((unsigned long)cr & 0x00000400))
325 continue; /* disabled */
326 ram_base = (unsigned long)(cr >> 49) << 21;
327 ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
328 if (ram_base >= 0x20000000)
329 continue; /* high memory (ignore) */
330 printk(" CR%d:%016Lx", i, cr);
331 tx4938_sdram_resource[i].name = "SDRAM";
332 tx4938_sdram_resource[i].start = ram_base;
333 tx4938_sdram_resource[i].end = ram_base + ram_size - 1;
334 tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
335 request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
337 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr);
340 if (tx4938_sramcptr->cr & 1) {
341 unsigned int size = 0x800;
343 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1);
344 tx4938_sram_resource.name = "SRAM";
345 tx4938_sram_resource.start = base;
346 tx4938_sram_resource.end = base + size - 1;
347 tx4938_sram_resource.flags = IORESOURCE_MEM;
348 request_resource(&iomem_resource, &tx4938_sram_resource);
352 for (i = 0; i < TX4938_NR_TMR; i++)
353 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
356 for (i = 0; i < 2; i++)
357 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
358 (void __iomem *)(TX4938_DMA_REG(i) + 0x50));
361 __raw_writel(0, &tx4938_pioptr->maskcpu);
362 __raw_writel(0, &tx4938_pioptr->maskext);
365 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
369 void __init plat_time_init(void)
371 mips_hpt_frequency = txx9_cpu_clock / 2;
372 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS)
373 txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL,
374 TXX9_IRQ_BASE + TX4938_IR_TMR(0),
375 txx9_gbus_clock / 2);
378 void __init plat_mem_setup(void)
380 unsigned long long pcfg;
383 iomem_resource.end = 0xffffffff; /* 4GB */
385 if (txx9_master_clock == 0)
386 txx9_master_clock = 25000000; /* 25MHz */
387 tx4938_board_setup();
389 set_io_port_base(RBTX4938_ETHER_BASE);
392 #ifdef CONFIG_SERIAL_TXX9
394 extern int early_serial_txx9_setup(struct uart_port *port);
396 struct uart_port req;
397 for(i = 0; i < 2; i++) {
398 memset(&req, 0, sizeof(req));
400 req.iotype = UPIO_MEM;
401 req.membase = (char *)(0xff1ff300 + i * 0x100);
402 req.mapbase = 0xff1ff300 + i * 0x100;
403 req.irq = RBTX4938_IRQ_IRC_SIO(i);
404 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
405 req.uartclk = 50000000;
406 early_serial_txx9_setup(&req);
409 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
410 argptr = prom_getcmdline();
411 if (strstr(argptr, "console=") == NULL) {
412 strcat(argptr, " console=ttyS0,38400");
417 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
418 printk("PIOSEL: disabling both ata and nand selection\n");
420 txx9_clear64(&tx4938_ccfgptr->pcfg,
421 TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
424 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
425 printk("PIOSEL: enabling nand selection\n");
426 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
427 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
430 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
431 printk("PIOSEL: enabling ata selection\n");
432 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
433 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
437 argptr = prom_getcmdline();
438 if (strstr(argptr, "ip=") == NULL) {
439 strcat(argptr, " ip=any");
446 conswitchp = &dummy_con;
450 rbtx4938_spi_setup();
451 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */
453 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
455 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04,
456 rbtx4938_piosel_addr);
457 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
459 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08,
460 rbtx4938_piosel_addr);
462 writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04),
463 rbtx4938_piosel_addr);
465 rbtx4938_fpga_resource.name = "FPGA Registers";
466 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
467 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
468 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
469 if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))
470 printk("request resource for fpga failed\n");
472 _machine_restart = rbtx4938_machine_restart;
473 _machine_halt = rbtx4938_machine_halt;
474 pm_power_off = rbtx4938_machine_power_off;
476 writeb(0xff, rbtx4938_led_addr);
477 printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
478 readb(rbtx4938_fpga_rev_addr),
479 readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
482 static int __init rbtx4938_ne_init(void)
484 struct resource res[] = {
486 .start = RBTX4938_RTL_8019_BASE,
487 .end = RBTX4938_RTL_8019_BASE + 0x20 - 1,
488 .flags = IORESOURCE_IO,
490 .start = RBTX4938_RTL_8019_IRQ,
491 .flags = IORESOURCE_IRQ,
494 struct platform_device *dev =
495 platform_device_register_simple("ne", -1,
496 res, ARRAY_SIZE(res));
497 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
499 device_initcall(rbtx4938_ne_init);
503 int gpio_to_irq(unsigned gpio)
508 int irq_to_gpio(unsigned irq)
513 static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
515 static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
520 spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
521 val = readb(rbtx4938_spics_addr);
525 val &= ~(1 << offset);
526 writeb(val, rbtx4938_spics_addr);
528 spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
531 static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip,
532 unsigned int offset, int value)
534 rbtx4938_spi_gpio_set(chip, offset, value);
538 static struct gpio_chip rbtx4938_spi_gpio_chip = {
539 .set = rbtx4938_spi_gpio_set,
540 .direction_output = rbtx4938_spi_gpio_dir_out,
541 .label = "RBTX4938-SPICS",
548 static void __init txx9_spi_init(unsigned long base, int irq)
550 struct resource res[] = {
553 .end = base + 0x20 - 1,
554 .flags = IORESOURCE_MEM,
557 .flags = IORESOURCE_IRQ,
560 platform_device_register_simple("spi_txx9", 0,
561 res, ARRAY_SIZE(res));
564 static int __init rbtx4938_spi_init(void)
566 struct spi_board_info srtc_info = {
567 .modalias = "rtc-rs5c348",
568 .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
570 .chip_select = 16 + SRTC_CS,
571 /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */
572 .mode = SPI_MODE_1 | SPI_CS_HIGH,
574 spi_register_board_info(&srtc_info, 1);
575 spi_eeprom_register(SEEPROM1_CS);
576 spi_eeprom_register(16 + SEEPROM2_CS);
577 spi_eeprom_register(16 + SEEPROM3_CS);
578 gpio_request(16 + SRTC_CS, "rtc-rs5c348");
579 gpio_direction_output(16 + SRTC_CS, 0);
580 gpio_request(SEEPROM1_CS, "seeprom1");
581 gpio_direction_output(SEEPROM1_CS, 1);
582 gpio_request(16 + SEEPROM2_CS, "seeprom2");
583 gpio_direction_output(16 + SEEPROM2_CS, 1);
584 gpio_request(16 + SEEPROM3_CS, "seeprom3");
585 gpio_direction_output(16 + SEEPROM3_CS, 1);
586 txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI);
590 static int __init rbtx4938_arch_init(void)
592 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16);
593 gpiochip_add(&rbtx4938_spi_gpio_chip);
594 rbtx4938_pci_setup();
595 return rbtx4938_spi_init();
597 arch_initcall(rbtx4938_arch_init);
599 /* Watchdog support */
601 static int __init txx9_wdt_init(unsigned long base)
603 struct resource res = {
605 .end = base + 0x100 - 1,
606 .flags = IORESOURCE_MEM,
608 struct platform_device *dev =
609 platform_device_register_simple("txx9wdt", -1, &res, 1);
610 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
613 static int __init rbtx4938_wdt_init(void)
615 return txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL);
617 device_initcall(rbtx4938_wdt_init);
619 /* Minimum CLK support */
621 struct clk *clk_get(struct device *dev, const char *id)
623 if (!strcmp(id, "spi-baseclk"))
624 return (struct clk *)(txx9_gbus_clock / 2 / 4);
625 if (!strcmp(id, "imbus_clk"))
626 return (struct clk *)(txx9_gbus_clock / 2);
627 return ERR_PTR(-ENOENT);
629 EXPORT_SYMBOL(clk_get);
631 int clk_enable(struct clk *clk)
635 EXPORT_SYMBOL(clk_enable);
637 void clk_disable(struct clk *clk)
640 EXPORT_SYMBOL(clk_disable);
642 unsigned long clk_get_rate(struct clk *clk)
644 return (unsigned long)clk;
646 EXPORT_SYMBOL(clk_get_rate);
648 void clk_put(struct clk *clk)
651 EXPORT_SYMBOL(clk_put);