2 * Toshiba RBTX4938 specific interrupt handlers
3 * Copyright (C) 2000-2001 Toshiba Corporation
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
16 16 TX4938-CP0/00 Software 0
17 17 TX4938-CP0/01 Software 1
18 18 TX4938-CP0/02 Cascade TX4938-CP0
19 19 TX4938-CP0/03 Multiplexed -- do not use
20 20 TX4938-CP0/04 Multiplexed -- do not use
21 21 TX4938-CP0/05 Multiplexed -- do not use
22 22 TX4938-CP0/06 Multiplexed -- do not use
23 23 TX4938-CP0/07 CPU TIMER
27 26 TX4938-PIC/02 Cascade RBTX4938-IOC
28 27 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet
30 29 TX4938-PIC/05 TX4938 ETH1
31 30 TX4938-PIC/06 TX4938 ETH0
33 32 TX4938-PIC/08 TX4938 SIO 0
34 33 TX4938-PIC/09 TX4938 SIO 1
35 34 TX4938-PIC/10 TX4938 DMA0
36 35 TX4938-PIC/11 TX4938 DMA1
37 36 TX4938-PIC/12 TX4938 DMA2
38 37 TX4938-PIC/13 TX4938 DMA3
41 40 TX4938-PIC/16 TX4938 PCIC
42 41 TX4938-PIC/17 TX4938 TMR0
43 42 TX4938-PIC/18 TX4938 TMR1
44 43 TX4938-PIC/19 TX4938 TMR2
47 46 TX4938-PIC/22 TX4938 PCIERR
56 55 TX4938-PIC/31 TX4938 SPI
58 56 RBTX4938-IOC/00 PCI-D
59 57 RBTX4938-IOC/01 PCI-C
60 58 RBTX4938-IOC/02 PCI-B
61 59 RBTX4938-IOC/03 PCI-A
62 60 RBTX4938-IOC/04 RTC
63 61 RBTX4938-IOC/05 ATA
64 62 RBTX4938-IOC/06 MODEM
65 63 RBTX4938-IOC/07 SWINT
67 #include <linux/init.h>
68 #include <linux/interrupt.h>
69 #include <asm/txx9/rbtx4938.h>
71 static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
72 static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
74 #define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
75 static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
76 .name = TOSHIBA_RBTX4938_IOC_NAME,
77 .ack = toshiba_rbtx4938_irq_ioc_disable,
78 .mask = toshiba_rbtx4938_irq_ioc_disable,
79 .mask_ack = toshiba_rbtx4938_irq_ioc_disable,
80 .unmask = toshiba_rbtx4938_irq_ioc_enable,
84 toshiba_rbtx4938_irq_nested(int sw_irq)
88 level3 = readb(rbtx4938_imstat_addr);
90 /* must use fls so onboard ATA has priority */
91 sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1;
96 static struct irqaction toshiba_rbtx4938_irq_ioc_action = {
99 .mask = CPU_MASK_NONE,
100 .name = TOSHIBA_RBTX4938_IOC_NAME,
103 /**********************************************************************************/
104 /* Functions for ioc */
105 /**********************************************************************************/
107 toshiba_rbtx4938_irq_ioc_init(void)
111 for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG;
112 i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++)
113 set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
116 setup_irq(RBTX4938_IRQ_IOCINT,
117 &toshiba_rbtx4938_irq_ioc_action);
121 toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
125 v = readb(rbtx4938_imask_addr);
126 v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
127 writeb(v, rbtx4938_imask_addr);
132 toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
136 v = readb(rbtx4938_imask_addr);
137 v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
138 writeb(v, rbtx4938_imask_addr);
142 void __init arch_init_irq(void)
144 extern void tx4938_irq_init(void);
146 /* Now, interrupt control disabled, */
147 /* all IRC interrupts are masked, */
148 /* all IRC interrupt mode are Low Active. */
150 /* mask all IOC interrupts */
151 writeb(0, rbtx4938_imask_addr);
153 /* clear SoftInt interrupts */
154 writeb(0, rbtx4938_softint_addr);
156 toshiba_rbtx4938_irq_ioc_init();
157 /* Onboard 10M Ether: High Active */
158 set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);