2 * Toshiba rbtx4927 specific setup
4 * Author: MontaVista Software, Inc.
7 * Copyright 2001-2002 MontaVista Software Inc.
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
10 * Copyright (C) 2000 RidgeRun, Inc.
11 * Author: RidgeRun, Inc.
12 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
14 * Copyright 2001 MontaVista Software Inc.
15 * Author: jsun@mvista.com or jsun@junsun.net
17 * Copyright 2002 MontaVista Software Inc.
18 * Author: Michael Pruznick, michael_pruznick@mvista.com
20 * Copyright (C) 2000-2001 Toshiba Corporation
22 * Copyright (C) 2004 MontaVista Software Inc.
23 * Author: Manish Lachwani, mlachwani@mvista.com
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms of the GNU General Public License as published by the
27 * Free Software Foundation; either version 2 of the License, or (at your
28 * option) any later version.
30 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
31 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
35 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
36 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
38 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
39 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * You should have received a copy of the GNU General Public License along
42 * with this program; if not, write to the Free Software Foundation, Inc.,
43 * 675 Mass Ave, Cambridge, MA 02139, USA.
45 #include <linux/init.h>
46 #include <linux/kernel.h>
47 #include <linux/types.h>
48 #include <linux/ioport.h>
49 #include <linux/interrupt.h>
51 #include <linux/platform_device.h>
52 #include <linux/delay.h>
54 #include <asm/bootinfo.h>
56 #include <asm/processor.h>
57 #include <asm/reboot.h>
59 #include <asm/txx9tmr.h>
60 #include <asm/txx9/generic.h>
61 #include <asm/txx9/pci.h>
62 #include <asm/txx9/rbtx4927.h>
63 #include <asm/txx9/tx4938.h> /* for TX4937 */
64 #ifdef CONFIG_SERIAL_TXX9
65 #include <linux/serial_core.h>
68 /* These functions are used for rebooting or halting the machine*/
69 extern void toshiba_rbtx4927_restart(char *command);
70 extern void toshiba_rbtx4927_halt(void);
71 extern void toshiba_rbtx4927_power_off(void);
72 extern void toshiba_rbtx4927_irq_setup(void);
74 char *prom_getcmdline(void);
76 static int tx4927_ccfg_toeon = 1;
79 static void __init tx4927_pci_setup(void)
81 int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB);
82 struct pci_controller *c = &txx9_primary_pcic;
84 register_pci_controller(c);
86 if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66)
88 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
89 TXX9_PCI_OPT_CLK_66; /* already configured */
92 writeb(1, rbtx4927_pcireset_addr);
94 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
95 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
97 tx4927_pciclk66_setup();
99 /* clear PCIC reset */
100 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
101 writeb(0, rbtx4927_pcireset_addr);
104 tx4927_report_pciclk();
105 tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
106 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
107 TXX9_PCI_OPT_CLK_AUTO &&
108 txx9_pci66_check(c, 0, 0)) {
110 writeb(1, rbtx4927_pcireset_addr);
112 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
113 tx4927_pciclk66_setup();
115 /* clear PCIC reset */
116 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
117 writeb(0, rbtx4927_pcireset_addr);
119 /* Reinitialize PCIC */
120 tx4927_report_pciclk();
121 tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
125 static void __init tx4937_pci_setup(void)
127 int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
128 struct pci_controller *c = &txx9_primary_pcic;
130 register_pci_controller(c);
132 if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
134 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
135 TXX9_PCI_OPT_CLK_66; /* already configured */
138 writeb(1, rbtx4927_pcireset_addr);
140 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
141 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
143 tx4938_pciclk66_setup();
145 /* clear PCIC reset */
146 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
147 writeb(0, rbtx4927_pcireset_addr);
150 tx4938_report_pciclk();
151 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
152 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
153 TXX9_PCI_OPT_CLK_AUTO &&
154 txx9_pci66_check(c, 0, 0)) {
156 writeb(1, rbtx4927_pcireset_addr);
158 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
159 tx4938_pciclk66_setup();
161 /* clear PCIC reset */
162 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
163 writeb(0, rbtx4927_pcireset_addr);
165 /* Reinitialize PCIC */
166 tx4938_report_pciclk();
167 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
171 static void __init rbtx4927_arch_init(void)
176 static void __init rbtx4937_arch_init(void)
181 #define rbtx4927_arch_init NULL
182 #define rbtx4937_arch_init NULL
183 #endif /* CONFIG_PCI */
185 static void __noreturn wait_forever(void)
192 void toshiba_rbtx4927_restart(char *command)
194 printk(KERN_NOTICE "System Rebooting...\n");
196 /* enable the s/w reset register */
197 writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE);
199 /* wait for enable to be seen */
200 while ((readb(RBTX4927_SW_RESET_ENABLE) &
201 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
204 writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO);
206 /* do something passive while waiting for reset */
212 void toshiba_rbtx4927_halt(void)
214 printk(KERN_NOTICE "System Halted\n");
220 void toshiba_rbtx4927_power_off(void)
222 toshiba_rbtx4927_halt();
226 static void __init rbtx4927_mem_setup(void)
232 /* f/w leaves this on at startup */
233 clear_c0_status(ST0_ERL);
235 /* enable caches -- HCP5 does this, pmon does not */
236 cp0_config = read_c0_config();
237 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
238 write_c0_config(cp0_config);
240 ioport_resource.end = 0xffffffff;
241 iomem_resource.end = 0xffffffff;
243 _machine_restart = toshiba_rbtx4927_restart;
244 _machine_halt = toshiba_rbtx4927_halt;
245 pm_power_off = toshiba_rbtx4927_power_off;
247 for (i = 0; i < TX4927_NR_TMR; i++)
248 txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
251 txx9_alloc_pci_controller(&txx9_primary_pcic,
252 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
253 RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
255 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
259 /* do reset on watchdog */
260 tx4927_ccfg_set(TX4927_CCFG_WR);
261 /* enable Timeout BusError */
262 if (tx4927_ccfg_toeon)
263 tx4927_ccfg_set(TX4927_CCFG_TOE);
265 #ifdef CONFIG_SERIAL_TXX9
267 extern int early_serial_txx9_setup(struct uart_port *port);
268 struct uart_port req;
269 for(i = 0; i < 2; i++) {
270 memset(&req, 0, sizeof(req));
272 req.iotype = UPIO_MEM;
273 req.membase = (char *)(0xff1ff300 + i * 0x100);
274 req.mapbase = 0xff1ff300 + i * 0x100;
275 req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i);
276 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
277 req.uartclk = 50000000;
278 early_serial_txx9_setup(&req);
281 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
282 argptr = prom_getcmdline();
283 if (strstr(argptr, "console=") == NULL) {
284 strcat(argptr, " console=ttyS0,38400");
289 #ifdef CONFIG_ROOT_NFS
290 argptr = prom_getcmdline();
291 if (strstr(argptr, "root=") == NULL) {
292 strcat(argptr, " root=/dev/nfs rw");
297 argptr = prom_getcmdline();
298 if (strstr(argptr, "ip=") == NULL) {
299 strcat(argptr, " ip=any");
304 static void __init rbtx4927_time_init(void)
307 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
310 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
311 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
312 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
313 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
314 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
315 * i.e. S9[3]: ON (83MHz), OFF (100MHz)
318 * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
319 * PCIDIVMODE[10] is 0.
320 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
321 * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
322 * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
323 * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
324 * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
325 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
327 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
328 switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) &
329 TX4938_CCFG_PCIDIVMODE_MASK) {
330 case TX4938_CCFG_PCIDIVMODE_8:
331 case TX4938_CCFG_PCIDIVMODE_4:
332 txx9_cpu_clock = 266666666; /* 266MHz */
334 case TX4938_CCFG_PCIDIVMODE_9:
335 case TX4938_CCFG_PCIDIVMODE_4_5:
336 txx9_cpu_clock = 300000000; /* 300MHz */
339 txx9_cpu_clock = 333333333; /* 333MHz */
342 switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) &
343 TX4927_CCFG_PCIDIVMODE_MASK) {
344 case TX4927_CCFG_PCIDIVMODE_2_5:
345 case TX4927_CCFG_PCIDIVMODE_5:
346 txx9_cpu_clock = 166666666; /* 166MHz */
349 txx9_cpu_clock = 200000000; /* 200MHz */
352 /* change default value to udelay/mdelay take reasonable time */
353 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
355 mips_hpt_frequency = txx9_cpu_clock / 2;
356 if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
357 txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
362 static int __init toshiba_rbtx4927_rtc_init(void)
364 static struct resource __initdata res = {
366 .end = 0x1c010000 + 0x800 - 1,
367 .flags = IORESOURCE_MEM,
369 struct platform_device *dev =
370 platform_device_register_simple("rtc-ds1742", -1, &res, 1);
371 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
374 static int __init rbtx4927_ne_init(void)
376 static struct resource __initdata res[] = {
378 .start = RBTX4927_RTL_8019_BASE,
379 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
380 .flags = IORESOURCE_IO,
382 .start = RBTX4927_RTL_8019_IRQ,
383 .flags = IORESOURCE_IRQ,
386 struct platform_device *dev =
387 platform_device_register_simple("ne", -1,
388 res, ARRAY_SIZE(res));
389 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
392 /* Watchdog support */
394 static int __init txx9_wdt_init(unsigned long base)
396 struct resource res = {
398 .end = base + 0x100 - 1,
399 .flags = IORESOURCE_MEM,
401 struct platform_device *dev =
402 platform_device_register_simple("txx9wdt", -1, &res, 1);
403 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
406 static int __init rbtx4927_wdt_init(void)
408 return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
411 static void __init rbtx4927_device_init(void)
413 toshiba_rbtx4927_rtc_init();
418 struct txx9_board_vec rbtx4927_vec __initdata = {
419 .type = MACH_TOSHIBA_RBTX4927,
420 .system = "Toshiba RBTX4927",
421 .prom_init = rbtx4927_prom_init,
422 .mem_setup = rbtx4927_mem_setup,
423 .irq_setup = rbtx4927_irq_setup,
424 .time_init = rbtx4927_time_init,
425 .device_init = rbtx4927_device_init,
426 .arch_init = rbtx4927_arch_init,
428 .pci_map_irq = rbtx4927_pci_map_irq,
431 struct txx9_board_vec rbtx4937_vec __initdata = {
432 .type = MACH_TOSHIBA_RBTX4937,
433 .system = "Toshiba RBTX4937",
434 .prom_init = rbtx4927_prom_init,
435 .mem_setup = rbtx4927_mem_setup,
436 .irq_setup = rbtx4927_irq_setup,
437 .time_init = rbtx4927_time_init,
438 .device_init = rbtx4927_device_init,
439 .arch_init = rbtx4937_arch_init,
441 .pci_map_irq = rbtx4927_pci_map_irq,