2 * Toshiba rbtx4927 specific setup
4 * Author: MontaVista Software, Inc.
7 * Copyright 2001-2002 MontaVista Software Inc.
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
10 * Copyright (C) 2000 RidgeRun, Inc.
11 * Author: RidgeRun, Inc.
12 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
14 * Copyright 2001 MontaVista Software Inc.
15 * Author: jsun@mvista.com or jsun@junsun.net
17 * Copyright 2002 MontaVista Software Inc.
18 * Author: Michael Pruznick, michael_pruznick@mvista.com
20 * Copyright (C) 2000-2001 Toshiba Corporation
22 * Copyright (C) 2004 MontaVista Software Inc.
23 * Author: Manish Lachwani, mlachwani@mvista.com
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms of the GNU General Public License as published by the
27 * Free Software Foundation; either version 2 of the License, or (at your
28 * option) any later version.
30 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
31 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
35 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
36 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
38 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
39 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * You should have received a copy of the GNU General Public License along
42 * with this program; if not, write to the Free Software Foundation, Inc.,
43 * 675 Mass Ave, Cambridge, MA 02139, USA.
45 #include <linux/init.h>
46 #include <linux/kernel.h>
47 #include <linux/types.h>
48 #include <linux/ioport.h>
49 #include <linux/interrupt.h>
50 #include <linux/platform_device.h>
51 #include <linux/delay.h>
53 #include <asm/reboot.h>
54 #include <asm/txx9/generic.h>
55 #include <asm/txx9/pci.h>
56 #include <asm/txx9/rbtx4927.h>
57 #include <asm/txx9/tx4938.h> /* for TX4937 */
60 static void __init tx4927_pci_setup(void)
62 int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB);
63 struct pci_controller *c = &txx9_primary_pcic;
65 register_pci_controller(c);
67 if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66)
69 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
70 TXX9_PCI_OPT_CLK_66; /* already configured */
73 writeb(1, rbtx4927_pcireset_addr);
75 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
76 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
78 tx4927_pciclk66_setup();
80 /* clear PCIC reset */
81 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
82 writeb(0, rbtx4927_pcireset_addr);
85 tx4927_report_pciclk();
86 tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
87 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
88 TXX9_PCI_OPT_CLK_AUTO &&
89 txx9_pci66_check(c, 0, 0)) {
91 writeb(1, rbtx4927_pcireset_addr);
93 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
94 tx4927_pciclk66_setup();
96 /* clear PCIC reset */
97 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
98 writeb(0, rbtx4927_pcireset_addr);
100 /* Reinitialize PCIC */
101 tx4927_report_pciclk();
102 tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
104 tx4927_setup_pcierr_irq();
107 static void __init tx4937_pci_setup(void)
109 int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
110 struct pci_controller *c = &txx9_primary_pcic;
112 register_pci_controller(c);
114 if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
116 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
117 TXX9_PCI_OPT_CLK_66; /* already configured */
120 writeb(1, rbtx4927_pcireset_addr);
122 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
123 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
125 tx4938_pciclk66_setup();
127 /* clear PCIC reset */
128 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
129 writeb(0, rbtx4927_pcireset_addr);
132 tx4938_report_pciclk();
133 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
134 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
135 TXX9_PCI_OPT_CLK_AUTO &&
136 txx9_pci66_check(c, 0, 0)) {
138 writeb(1, rbtx4927_pcireset_addr);
140 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
141 tx4938_pciclk66_setup();
143 /* clear PCIC reset */
144 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
145 writeb(0, rbtx4927_pcireset_addr);
147 /* Reinitialize PCIC */
148 tx4938_report_pciclk();
149 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
151 tx4938_setup_pcierr_irq();
154 static void __init rbtx4927_arch_init(void)
159 static void __init rbtx4937_arch_init(void)
164 #define rbtx4927_arch_init NULL
165 #define rbtx4937_arch_init NULL
166 #endif /* CONFIG_PCI */
168 static void toshiba_rbtx4927_restart(char *command)
170 /* enable the s/w reset register */
171 writeb(1, rbtx4927_softresetlock_addr);
173 /* wait for enable to be seen */
174 while (!(readb(rbtx4927_softresetlock_addr) & 1))
178 writeb(1, rbtx4927_softreset_addr);
184 static void __init rbtx4927_clock_init(void);
185 static void __init rbtx4937_clock_init(void);
187 static void __init rbtx4927_mem_setup(void)
192 /* f/w leaves this on at startup */
193 clear_c0_status(ST0_ERL);
195 /* enable caches -- HCP5 does this, pmon does not */
196 cp0_config = read_c0_config();
197 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
198 write_c0_config(cp0_config);
200 if (TX4927_REV_PCODE() == 0x4927) {
201 rbtx4927_clock_init();
204 rbtx4937_clock_init();
208 _machine_restart = toshiba_rbtx4927_restart;
211 txx9_alloc_pci_controller(&txx9_primary_pcic,
212 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
213 RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
214 txx9_board_pcibios_setup = tx4927_pcibios_setup;
216 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
219 tx4927_setup_serial();
220 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
221 argptr = prom_getcmdline();
222 if (strstr(argptr, "console=") == NULL) {
223 strcat(argptr, " console=ttyS0,38400");
227 #ifdef CONFIG_ROOT_NFS
228 argptr = prom_getcmdline();
229 if (strstr(argptr, "root=") == NULL) {
230 strcat(argptr, " root=/dev/nfs rw");
235 argptr = prom_getcmdline();
236 if (strstr(argptr, "ip=") == NULL) {
237 strcat(argptr, " ip=any");
242 static void __init rbtx4927_clock_init(void)
245 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
248 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
249 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
250 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
251 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
252 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
253 * i.e. S9[3]: ON (83MHz), OFF (100MHz)
255 switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) &
256 TX4927_CCFG_PCIDIVMODE_MASK) {
257 case TX4927_CCFG_PCIDIVMODE_2_5:
258 case TX4927_CCFG_PCIDIVMODE_5:
259 txx9_cpu_clock = 166666666; /* 166MHz */
262 txx9_cpu_clock = 200000000; /* 200MHz */
266 static void __init rbtx4937_clock_init(void)
269 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
272 * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
273 * PCIDIVMODE[10] is 0.
274 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
275 * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
276 * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
277 * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
278 * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
279 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
281 switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) &
282 TX4938_CCFG_PCIDIVMODE_MASK) {
283 case TX4938_CCFG_PCIDIVMODE_8:
284 case TX4938_CCFG_PCIDIVMODE_4:
285 txx9_cpu_clock = 266666666; /* 266MHz */
287 case TX4938_CCFG_PCIDIVMODE_9:
288 case TX4938_CCFG_PCIDIVMODE_4_5:
289 txx9_cpu_clock = 300000000; /* 300MHz */
292 txx9_cpu_clock = 333333333; /* 333MHz */
296 static void __init rbtx4927_time_init(void)
301 static int __init toshiba_rbtx4927_rtc_init(void)
303 struct resource res = {
304 .start = RBTX4927_BRAMRTC_BASE - IO_BASE,
305 .end = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1,
306 .flags = IORESOURCE_MEM,
308 struct platform_device *dev =
309 platform_device_register_simple("rtc-ds1742", -1, &res, 1);
310 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
313 static int __init rbtx4927_ne_init(void)
315 struct resource res[] = {
317 .start = RBTX4927_RTL_8019_BASE,
318 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
319 .flags = IORESOURCE_IO,
321 .start = RBTX4927_RTL_8019_IRQ,
322 .flags = IORESOURCE_IRQ,
325 struct platform_device *dev =
326 platform_device_register_simple("ne", -1,
327 res, ARRAY_SIZE(res));
328 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
331 static void __init rbtx4927_device_init(void)
333 toshiba_rbtx4927_rtc_init();
338 struct txx9_board_vec rbtx4927_vec __initdata = {
339 .system = "Toshiba RBTX4927",
340 .prom_init = rbtx4927_prom_init,
341 .mem_setup = rbtx4927_mem_setup,
342 .irq_setup = rbtx4927_irq_setup,
343 .time_init = rbtx4927_time_init,
344 .device_init = rbtx4927_device_init,
345 .arch_init = rbtx4927_arch_init,
347 .pci_map_irq = rbtx4927_pci_map_irq,
350 struct txx9_board_vec rbtx4937_vec __initdata = {
351 .system = "Toshiba RBTX4937",
352 .prom_init = rbtx4927_prom_init,
353 .mem_setup = rbtx4927_mem_setup,
354 .irq_setup = rbtx4927_irq_setup,
355 .time_init = rbtx4927_time_init,
356 .device_init = rbtx4927_device_init,
357 .arch_init = rbtx4937_arch_init,
359 .pci_map_irq = rbtx4927_pci_map_irq,