2 * Toshiba RBTX4927 specific interrupt handlers
4 * Author: MontaVista Software, Inc.
7 * Copyright 2001-2002 MontaVista Software Inc.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
20 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
21 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
22 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
23 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 01 RBTX4927-ISA/01 PS2/Keyboard
33 02 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15)
43 12 RBTX4927-ISA/12 PS2/Mouse (not supported at this time)
45 14 RBTX4927-ISA/14 IDE
48 16 TX4927-CP0/00 Software 0
49 17 TX4927-CP0/01 Software 1
50 18 TX4927-CP0/02 Cascade TX4927-CP0
51 19 TX4927-CP0/03 Multiplexed -- do not use
52 20 TX4927-CP0/04 Multiplexed -- do not use
53 21 TX4927-CP0/05 Multiplexed -- do not use
54 22 TX4927-CP0/06 Multiplexed -- do not use
55 23 TX4927-CP0/07 CPU TIMER
60 27 TX4927-PIC/03 Cascade RBTX4927-IOC
62 29 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet
65 32 TX4927-PIC/08 TX4927 SerialIO Channel 0
66 33 TX4927-PIC/09 TX4927 SerialIO Channel 1
73 40 TX4927-PIC/16 TX4927 PCI PCI-C
79 46 TX4927-PIC/22 TX4927 PCI PCI-ERR
80 47 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used)
90 56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed) [RTL-8139=PJ4]
91 57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed) [RTL-8139=PJ5]
92 58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported]
93 59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4) [RTL-8139=PJ6]
100 SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
101 SouthBridge/ISA/pin=0 no pci irq used by this device
102 SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14
103 SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59
104 SouthBridge/PMC/pin=0 no pci irq used by this device
105 SuperIO/PS2/Keyboard, using INTR via ISA IRQ1
106 SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported)
107 JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6
110 #include <linux/init.h>
111 #include <linux/types.h>
112 #include <linux/interrupt.h>
114 #ifdef CONFIG_TOSHIBA_FPCIB0
115 #include <asm/i8259.h>
117 #include <asm/txx9/rbtx4927.h>
119 #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0
120 #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7
122 #define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */
123 #define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */
125 #define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC
126 #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2)
128 extern int tx4927_using_backplane;
130 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
131 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
133 #define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
134 static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
135 .name = TOSHIBA_RBTX4927_IOC_NAME,
136 .ack = toshiba_rbtx4927_irq_ioc_disable,
137 .mask = toshiba_rbtx4927_irq_ioc_disable,
138 .mask_ack = toshiba_rbtx4927_irq_ioc_disable,
139 .unmask = toshiba_rbtx4927_irq_ioc_enable,
141 #define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL
142 #define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL
144 int toshiba_rbtx4927_irq_nested(int sw_irq)
148 level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
150 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1;
151 #ifdef CONFIG_TOSHIBA_FPCIB0
152 if (sw_irq == TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC &&
153 tx4927_using_backplane) {
154 int irq = i8259_irq();
163 static struct irqaction toshiba_rbtx4927_irq_ioc_action = {
164 .handler = no_action,
165 .flags = IRQF_SHARED,
166 .mask = CPU_MASK_NONE,
167 .name = TOSHIBA_RBTX4927_IOC_NAME
170 static void __init toshiba_rbtx4927_irq_ioc_init(void)
174 for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG;
175 i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++)
176 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
179 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
180 &toshiba_rbtx4927_irq_ioc_action);
183 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
187 v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
188 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
189 writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB);
192 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
196 v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
197 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
198 writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB);
202 void __init arch_init_irq(void)
204 extern void tx4927_irq_init(void);
207 toshiba_rbtx4927_irq_ioc_init();
208 #ifdef CONFIG_TOSHIBA_FPCIB0
209 if (tx4927_using_backplane)
212 /* Onboard 10M Ether: High Active */
213 set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH);