2 * TX4939 setup routines
3 * Based on linux/arch/mips/txx9/generic/setup_tx4938.c,
4 * and RBTX49xx patch from CELF patch archive.
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/delay.h>
16 #include <linux/netdevice.h>
17 #include <linux/notifier.h>
18 #include <linux/sysdev.h>
19 #include <linux/ethtool.h>
20 #include <linux/param.h>
21 #include <linux/ptrace.h>
22 #include <linux/mtd/physmap.h>
23 #include <asm/bootinfo.h>
24 #include <asm/reboot.h>
25 #include <asm/traps.h>
26 #include <asm/txx9irq.h>
27 #include <asm/txx9tmr.h>
28 #include <asm/txx9/generic.h>
29 #include <asm/txx9/tx4939.h>
31 static void __init tx4939_wdr_init(void)
33 /* report watchdog reset status */
34 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST)
35 pr_warning("Watchdog reset detected at 0x%lx\n",
37 /* clear WatchDogReset (W1C) */
38 tx4939_ccfg_set(TX4939_CCFG_WDRST);
39 /* do reset on watchdog */
40 tx4939_ccfg_set(TX4939_CCFG_WR);
43 void __init tx4939_wdt_init(void)
45 txx9_wdt_init(TX4939_TMR_REG(2) & 0xfffffffffULL);
48 static void tx4939_machine_restart(char *command)
51 pr_emerg("Rebooting (with %s watchdog reset)...\n",
52 (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) ?
53 "external" : "internal");
54 /* clear watchdog status */
55 tx4939_ccfg_set(TX4939_CCFG_WDRST); /* W1C */
56 txx9_wdt_now(TX4939_TMR_REG(2) & 0xfffffffffULL);
57 while (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST))
60 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) {
61 pr_emerg("Rebooting (with internal watchdog reset)...\n");
62 /* External WDRST failed. Do internal watchdog reset */
63 tx4939_ccfg_clear(TX4939_CCFG_WDREXEN);
69 void show_registers(struct pt_regs *regs);
70 static int tx4939_be_handler(struct pt_regs *regs, int is_fixup)
72 int data = regs->cp0_cause & 4;
74 pr_err("%cBE exception at %#lx\n",
75 data ? 'D' : 'I', regs->cp0_epc);
76 pr_err("ccfg:%llx, toea:%llx\n",
77 (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
78 (unsigned long long)____raw_readq(&tx4939_ccfgptr->toea));
80 tx4927_report_pcic_status();
85 static void __init tx4939_be_init(void)
87 board_be_handler = tx4939_be_handler;
90 static struct resource tx4939_sdram_resource[4];
91 static struct resource tx4939_sram_resource;
92 #define TX4939_SRAM_SIZE 0x800
94 void __init tx4939_add_memory_regions(void)
97 unsigned long start, size;
100 for (i = 0; i < 4; i++) {
101 if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
103 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
104 start = (unsigned long)(win >> 48);
105 size = (((unsigned long)(win >> 32) & 0xffff) + 1) - start;
106 add_memory_region(start << 20, size << 20, BOOT_MEM_RAM);
110 void __init tx4939_setup(void)
117 txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE,
119 set_c0_config(TX49_CONF_CWFON);
121 /* SDRAMC,EBUSC are configured by PROM */
122 for (i = 0; i < 4; i++) {
123 if (!(TX4939_EBUSC_CR(i) & 0x8))
124 continue; /* disabled */
125 txx9_ce_res[i].start = (unsigned long)TX4939_EBUSC_BA(i);
127 txx9_ce_res[i].start + TX4939_EBUSC_SIZE(i) - 1;
128 request_resource(&iomem_resource, &txx9_ce_res[i]);
132 if (txx9_master_clock) {
133 /* calculate cpu_clock from master_clock */
134 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
135 TX4939_CCFG_MULCLK_MASK;
136 cpuclk = txx9_master_clock * 20 / 2;
138 case TX4939_CCFG_MULCLK_8:
139 cpuclk = cpuclk / 3 * 4 /* / 6 * 8 */; break;
140 case TX4939_CCFG_MULCLK_9:
141 cpuclk = cpuclk / 2 * 3 /* / 6 * 9 */; break;
142 case TX4939_CCFG_MULCLK_10:
143 cpuclk = cpuclk / 3 * 5 /* / 6 * 10 */; break;
144 case TX4939_CCFG_MULCLK_11:
145 cpuclk = cpuclk / 6 * 11; break;
146 case TX4939_CCFG_MULCLK_12:
147 cpuclk = cpuclk * 2 /* / 6 * 12 */; break;
148 case TX4939_CCFG_MULCLK_13:
149 cpuclk = cpuclk / 6 * 13; break;
150 case TX4939_CCFG_MULCLK_14:
151 cpuclk = cpuclk / 3 * 7 /* / 6 * 14 */; break;
152 case TX4939_CCFG_MULCLK_15:
153 cpuclk = cpuclk / 2 * 5 /* / 6 * 15 */; break;
155 txx9_cpu_clock = cpuclk;
157 if (txx9_cpu_clock == 0)
158 txx9_cpu_clock = 400000000; /* 400MHz */
159 /* calculate master_clock from cpu_clock */
160 cpuclk = txx9_cpu_clock;
161 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
162 TX4939_CCFG_MULCLK_MASK;
164 case TX4939_CCFG_MULCLK_8:
165 txx9_master_clock = cpuclk * 6 / 8; break;
166 case TX4939_CCFG_MULCLK_9:
167 txx9_master_clock = cpuclk * 6 / 9; break;
168 case TX4939_CCFG_MULCLK_10:
169 txx9_master_clock = cpuclk * 6 / 10; break;
170 case TX4939_CCFG_MULCLK_11:
171 txx9_master_clock = cpuclk * 6 / 11; break;
172 case TX4939_CCFG_MULCLK_12:
173 txx9_master_clock = cpuclk * 6 / 12; break;
174 case TX4939_CCFG_MULCLK_13:
175 txx9_master_clock = cpuclk * 6 / 13; break;
176 case TX4939_CCFG_MULCLK_14:
177 txx9_master_clock = cpuclk * 6 / 14; break;
178 case TX4939_CCFG_MULCLK_15:
179 txx9_master_clock = cpuclk * 6 / 15; break;
181 txx9_master_clock /= 10; /* * 2 / 20 */
183 /* calculate gbus_clock from cpu_clock */
184 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
185 TX4939_CCFG_YDIVMODE_MASK;
186 txx9_gbus_clock = txx9_cpu_clock;
188 case TX4939_CCFG_YDIVMODE_2:
189 txx9_gbus_clock /= 2; break;
190 case TX4939_CCFG_YDIVMODE_3:
191 txx9_gbus_clock /= 3; break;
192 case TX4939_CCFG_YDIVMODE_5:
193 txx9_gbus_clock /= 5; break;
194 case TX4939_CCFG_YDIVMODE_6:
195 txx9_gbus_clock /= 6; break;
197 /* change default value to udelay/mdelay take reasonable time */
198 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
202 /* clear BusErrorOnWrite flag (W1C) */
203 tx4939_ccfg_set(TX4939_CCFG_WDRST | TX4939_CCFG_BEOW);
204 /* enable Timeout BusError */
206 tx4939_ccfg_set(TX4939_CCFG_TOE);
209 txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_DMASEL_ALL);
211 /* Use external clock for external arbiter */
212 if (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB))
213 txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_PCICLKEN_ALL);
215 pr_info("%s -- %dMHz(M%dMHz,G%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
217 (cpuclk + 500000) / 1000000,
218 (txx9_master_clock + 500000) / 1000000,
219 (txx9_gbus_clock + 500000) / 1000000,
220 (__u32)____raw_readq(&tx4939_ccfgptr->crir),
221 (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
222 (unsigned long long)____raw_readq(&tx4939_ccfgptr->pcfg));
224 pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
225 (__u32)____raw_readq(&tx4939_ddrcptr->winen));
226 for (i = 0; i < 4; i++) {
227 __u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
228 if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
229 continue; /* disabled */
230 printk(KERN_CONT " #%d:%016llx", i, (unsigned long long)win);
231 tx4939_sdram_resource[i].name = "DDR SDRAM";
232 tx4939_sdram_resource[i].start =
233 (unsigned long)(win >> 48) << 20;
234 tx4939_sdram_resource[i].end =
235 ((((unsigned long)(win >> 32) & 0xffff) + 1) <<
237 tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
238 request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
240 printk(KERN_CONT "\n");
243 if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
244 unsigned int size = TX4939_SRAM_SIZE;
245 tx4939_sram_resource.name = "SRAM";
246 tx4939_sram_resource.start =
247 (____raw_readq(&tx4939_sramcptr->cr) >> (39-11))
249 tx4939_sram_resource.end =
250 tx4939_sram_resource.start + TX4939_SRAM_SIZE - 1;
251 tx4939_sram_resource.flags = IORESOURCE_MEM;
252 request_resource(&iomem_resource, &tx4939_sram_resource);
256 /* disable all timers */
257 for (i = 0; i < TX4939_NR_TMR; i++)
258 txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL);
261 for (i = 0; i < 2; i++)
262 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
263 (void __iomem *)(TX4939_DMA_REG(i) + 0x50));
265 /* set PCIC1 reset (required to prevent hangup on BIST) */
266 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
267 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
268 if (pcfg & (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE)) {
269 mdelay(1); /* at least 128 cpu clock */
270 /* clear PCIC1 reset */
271 txx9_clear64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
273 pr_info("%s: stop PCIC1\n", txx9_pcode_str);
275 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1CKD);
277 if (!(pcfg & TX4939_PCFG_ET0MODE)) {
278 pr_info("%s: stop ETH0\n", txx9_pcode_str);
279 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0RST);
280 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0CKD);
282 if (!(pcfg & TX4939_PCFG_ET1MODE)) {
283 pr_info("%s: stop ETH1\n", txx9_pcode_str);
284 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1RST);
285 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1CKD);
288 _machine_restart = tx4939_machine_restart;
289 board_be_init = tx4939_be_init;
292 void __init tx4939_time_init(unsigned int tmrnr)
294 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_TINTDIS)
295 txx9_clockevent_init(TX4939_TMR_REG(tmrnr) & 0xfffffffffULL,
296 TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr),
300 void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
303 unsigned int ch_mask = 0;
304 __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
306 cts_mask |= ~1; /* only SIO0 have RTS/CTS */
307 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0)
308 cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */
309 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2)
310 ch_mask |= 1 << 2; /* disable SIO2 by PCFG setting */
311 if (pcfg & TX4939_PCFG_SIO3MODE)
312 ch_mask |= 1 << 3; /* disable SIO3 by PCFG setting */
313 for (i = 0; i < 4; i++) {
314 if ((1 << i) & ch_mask)
316 txx9_sio_init(TX4939_SIO_REG(i) & 0xfffffffffULL,
317 TXX9_IRQ_BASE + TX4939_IR_SIO(i),
318 i, sclk, (1 << i) & cts_mask);
322 #if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
323 static int tx4939_get_eth_speed(struct net_device *dev)
325 struct ethtool_cmd cmd = { ETHTOOL_GSET };
326 int speed = 100; /* default 100Mbps */
328 if (!dev->ethtool_ops || !dev->ethtool_ops->get_settings)
330 err = dev->ethtool_ops->get_settings(dev, &cmd);
333 speed = cmd.speed == SPEED_100 ? 100 : 10;
336 static int tx4939_netdev_event(struct notifier_block *this,
340 struct net_device *dev = ptr;
341 if (event == NETDEV_CHANGE && netif_carrier_ok(dev)) {
343 if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0))
344 bit = TX4939_PCFG_SPEED0;
345 else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1))
346 bit = TX4939_PCFG_SPEED1;
348 int speed = tx4939_get_eth_speed(dev);
350 txx9_set64(&tx4939_ccfgptr->pcfg, bit);
352 txx9_clear64(&tx4939_ccfgptr->pcfg, bit);
358 static struct notifier_block tx4939_netdev_notifier = {
359 .notifier_call = tx4939_netdev_event,
363 void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
365 u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
367 if (addr0 && (pcfg & TX4939_PCFG_ET0MODE))
368 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0);
369 if (addr1 && (pcfg & TX4939_PCFG_ET1MODE))
370 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1);
371 register_netdevice_notifier(&tx4939_netdev_notifier);
374 void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
379 void __init tx4939_mtd_init(int ch)
381 struct physmap_flash_data pdata = {
382 .width = TX4939_EBUSC_WIDTH(ch) / 8,
384 unsigned long start = txx9_ce_res[ch].start;
385 unsigned long size = txx9_ce_res[ch].end - start + 1;
387 if (!(TX4939_EBUSC_CR(ch) & 0x8))
388 return; /* disabled */
389 txx9_physmap_flash_init(ch, start, size, &pdata);
392 static void __init tx4939_stop_unused_modules(void)
394 __u64 pcfg, rst = 0, ckd = 0;
399 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
400 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
401 TX4939_PCFG_I2SMODE_ACLC) {
402 rst |= TX4939_CLKCTR_ACLRST;
403 ckd |= TX4939_CLKCTR_ACLCKD;
404 strcat(buf, " ACLC");
406 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
407 TX4939_PCFG_I2SMODE_I2S &&
408 (pcfg & TX4939_PCFG_I2SMODE_MASK) !=
409 TX4939_PCFG_I2SMODE_I2S_ALT) {
410 rst |= TX4939_CLKCTR_I2SRST;
411 ckd |= TX4939_CLKCTR_I2SCKD;
414 if (!(pcfg & TX4939_PCFG_ATA0MODE)) {
415 rst |= TX4939_CLKCTR_ATA0RST;
416 ckd |= TX4939_CLKCTR_ATA0CKD;
417 strcat(buf, " ATA0");
419 if (!(pcfg & TX4939_PCFG_ATA1MODE)) {
420 rst |= TX4939_CLKCTR_ATA1RST;
421 ckd |= TX4939_CLKCTR_ATA1CKD;
422 strcat(buf, " ATA1");
424 if (pcfg & TX4939_PCFG_SPIMODE) {
425 rst |= TX4939_CLKCTR_SPIRST;
426 ckd |= TX4939_CLKCTR_SPICKD;
429 if (!(pcfg & (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE))) {
430 rst |= TX4939_CLKCTR_VPCRST;
431 ckd |= TX4939_CLKCTR_VPCCKD;
434 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) {
435 rst |= TX4939_CLKCTR_SIO2RST;
436 ckd |= TX4939_CLKCTR_SIO2CKD;
437 strcat(buf, " SIO2");
439 if (pcfg & TX4939_PCFG_SIO3MODE) {
440 rst |= TX4939_CLKCTR_SIO3RST;
441 ckd |= TX4939_CLKCTR_SIO3CKD;
442 strcat(buf, " SIO3");
445 txx9_set64(&tx4939_ccfgptr->clkctr, rst);
446 txx9_set64(&tx4939_ccfgptr->clkctr, ckd);
450 pr_info("%s: stop%s\n", txx9_pcode_str, buf);
453 static int __init tx4939_late_init(void)
455 if (txx9_pcode != 0x4939)
457 tx4939_stop_unused_modules();
460 late_initcall(tx4939_late_init);