2 * TX4927 setup routines
3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
4 * and RBTX49xx patch from CELF patch archive.
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/delay.h>
16 #include <linux/param.h>
17 #include <linux/mtd/physmap.h>
18 #include <asm/txx9irq.h>
19 #include <asm/txx9tmr.h>
20 #include <asm/txx9pio.h>
21 #include <asm/txx9/generic.h>
22 #include <asm/txx9/tx4927.h>
24 static void __init tx4927_wdr_init(void)
26 /* clear WatchDogReset (W1C) */
27 tx4927_ccfg_set(TX4927_CCFG_WDRST);
28 /* do reset on watchdog */
29 tx4927_ccfg_set(TX4927_CCFG_WR);
32 void __init tx4927_wdt_init(void)
34 txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
37 static struct resource tx4927_sdram_resource[4];
39 void __init tx4927_setup(void)
46 txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,
48 set_c0_config(TX49_CONF_CWFON);
50 /* SDRAMC,EBUSC are configured by PROM */
51 for (i = 0; i < 8; i++) {
52 if (!(TX4927_EBUSC_CR(i) & 0x8))
53 continue; /* disabled */
54 txx9_ce_res[i].start = (unsigned long)TX4927_EBUSC_BA(i);
56 txx9_ce_res[i].start + TX4927_EBUSC_SIZE(i) - 1;
57 request_resource(&iomem_resource, &txx9_ce_res[i]);
61 ccfg = ____raw_readq(&tx4927_ccfgptr->ccfg);
62 if (txx9_master_clock) {
63 /* calculate gbus_clock and cpu_clock from master_clock */
64 divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
66 case TX4927_CCFG_DIVMODE_8:
67 case TX4927_CCFG_DIVMODE_10:
68 case TX4927_CCFG_DIVMODE_12:
69 case TX4927_CCFG_DIVMODE_16:
70 txx9_gbus_clock = txx9_master_clock * 4; break;
72 txx9_gbus_clock = txx9_master_clock;
75 case TX4927_CCFG_DIVMODE_2:
76 case TX4927_CCFG_DIVMODE_8:
77 cpuclk = txx9_gbus_clock * 2; break;
78 case TX4927_CCFG_DIVMODE_2_5:
79 case TX4927_CCFG_DIVMODE_10:
80 cpuclk = txx9_gbus_clock * 5 / 2; break;
81 case TX4927_CCFG_DIVMODE_3:
82 case TX4927_CCFG_DIVMODE_12:
83 cpuclk = txx9_gbus_clock * 3; break;
84 case TX4927_CCFG_DIVMODE_4:
85 case TX4927_CCFG_DIVMODE_16:
86 cpuclk = txx9_gbus_clock * 4; break;
88 txx9_cpu_clock = cpuclk;
90 if (txx9_cpu_clock == 0)
91 txx9_cpu_clock = 200000000; /* 200MHz */
92 /* calculate gbus_clock and master_clock from cpu_clock */
93 cpuclk = txx9_cpu_clock;
94 divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
96 case TX4927_CCFG_DIVMODE_2:
97 case TX4927_CCFG_DIVMODE_8:
98 txx9_gbus_clock = cpuclk / 2; break;
99 case TX4927_CCFG_DIVMODE_2_5:
100 case TX4927_CCFG_DIVMODE_10:
101 txx9_gbus_clock = cpuclk * 2 / 5; break;
102 case TX4927_CCFG_DIVMODE_3:
103 case TX4927_CCFG_DIVMODE_12:
104 txx9_gbus_clock = cpuclk / 3; break;
105 case TX4927_CCFG_DIVMODE_4:
106 case TX4927_CCFG_DIVMODE_16:
107 txx9_gbus_clock = cpuclk / 4; break;
110 case TX4927_CCFG_DIVMODE_8:
111 case TX4927_CCFG_DIVMODE_10:
112 case TX4927_CCFG_DIVMODE_12:
113 case TX4927_CCFG_DIVMODE_16:
114 txx9_master_clock = txx9_gbus_clock / 4; break;
116 txx9_master_clock = txx9_gbus_clock;
119 /* change default value to udelay/mdelay take reasonable time */
120 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
124 /* clear BusErrorOnWrite flag (W1C) */
125 tx4927_ccfg_set(TX4927_CCFG_BEOW);
126 /* enable Timeout BusError */
128 tx4927_ccfg_set(TX4927_CCFG_TOE);
131 txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_DMASEL_ALL);
133 /* Use external clock for external arbiter */
134 if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB))
135 txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL);
137 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
139 (cpuclk + 500000) / 1000000,
140 (txx9_master_clock + 500000) / 1000000,
141 (__u32)____raw_readq(&tx4927_ccfgptr->crir),
142 (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
143 (unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg));
145 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
146 for (i = 0; i < 4; i++) {
147 __u64 cr = TX4927_SDRAMC_CR(i);
148 unsigned long base, size;
149 if (!((__u32)cr & 0x00000400))
150 continue; /* disabled */
151 base = (unsigned long)(cr >> 49) << 21;
152 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
153 printk(" CR%d:%016llx", i, (unsigned long long)cr);
154 tx4927_sdram_resource[i].name = "SDRAM";
155 tx4927_sdram_resource[i].start = base;
156 tx4927_sdram_resource[i].end = base + size - 1;
157 tx4927_sdram_resource[i].flags = IORESOURCE_MEM;
158 request_resource(&iomem_resource, &tx4927_sdram_resource[i]);
160 printk(" TR:%09llx\n",
161 (unsigned long long)____raw_readq(&tx4927_sdramcptr->tr));
164 /* disable all timers */
165 for (i = 0; i < TX4927_NR_TMR; i++)
166 txx9_tmr_init(TX4927_TMR_REG(i) & 0xfffffffffULL);
169 txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO);
170 __raw_writel(0, &tx4927_pioptr->maskcpu);
171 __raw_writel(0, &tx4927_pioptr->maskext);
174 void __init tx4927_time_init(unsigned int tmrnr)
176 if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
177 txx9_clockevent_init(TX4927_TMR_REG(tmrnr) & 0xfffffffffULL,
178 TXX9_IRQ_BASE + TX4927_IR_TMR(tmrnr),
182 void __init tx4927_sio_init(unsigned int sclk, unsigned int cts_mask)
186 for (i = 0; i < 2; i++)
187 txx9_sio_init(TX4927_SIO_REG(i) & 0xfffffffffULL,
188 TXX9_IRQ_BASE + TX4927_IR_SIO(i),
189 i, sclk, (1 << i) & cts_mask);
192 void __init tx4927_mtd_init(int ch)
194 struct physmap_flash_data pdata = {
195 .width = TX4927_EBUSC_WIDTH(ch) / 8,
197 unsigned long start = txx9_ce_res[ch].start;
198 unsigned long size = txx9_ce_res[ch].end - start + 1;
200 if (!(TX4927_EBUSC_CR(ch) & 0x8))
201 return; /* disabled */
202 txx9_physmap_flash_init(ch, start, size, &pdata);