2 * linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c
4 * Setup pointers to hardware-dependent routines.
5 * Copyright (C) 2000-2001 Toshiba Corporation
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/ioport.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/console.h>
20 #include <linux/pci.h>
22 #include <linux/platform_device.h>
23 #include <linux/clk.h>
24 #include <linux/gpio.h>
26 #include <asm/wbflush.h>
27 #include <asm/reboot.h>
29 #include <asm/txx9tmr.h>
31 #include <asm/bootinfo.h>
32 #include <asm/tx4938/rbtx4938.h>
33 #ifdef CONFIG_SERIAL_TXX9
34 #include <linux/serial_core.h>
36 #include <linux/spi/spi.h>
37 #include <asm/tx4938/spi.h>
38 #include <asm/txx9pio.h>
40 extern char * __init prom_getcmdline(void);
41 static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr);
43 /* These functions are used for rebooting or halting the machine*/
44 extern void rbtx4938_machine_restart(char *command);
45 extern void rbtx4938_machine_halt(void);
46 extern void rbtx4938_machine_power_off(void);
49 unsigned int txx9_master_clock;
50 unsigned int txx9_cpu_clock;
51 unsigned int txx9_gbus_clock;
53 unsigned long rbtx4938_ce_base[8];
54 unsigned long rbtx4938_ce_size[8];
55 int txboard_pci66_mode;
56 static int tx4938_pcic_trdyto; /* default: disabled */
57 static int tx4938_pcic_retryto; /* default: disabled */
58 static int tx4938_ccfg_toeon = 1;
60 struct tx4938_pcic_reg *pcicptrs[4] = {
61 tx4938_pcicptr /* default setting for TX4938 */
67 } phys_regions[16] __initdata;
68 static int num_phys_regions __initdata;
70 #define PHYS_REGION_MINSIZE 0x10000
72 void rbtx4938_machine_halt(void)
74 printk(KERN_NOTICE "System Halted\n");
78 __asm__(".set\tmips3\n\t"
83 void rbtx4938_machine_power_off(void)
85 rbtx4938_machine_halt();
89 void rbtx4938_machine_restart(char *command)
93 printk("Rebooting...");
94 *rbtx4938_softresetlock_ptr = 1;
95 *rbtx4938_sfvol_ptr = 1;
96 *rbtx4938_softreset_ptr = 1;
103 txboard_add_phys_region(unsigned long base, unsigned long size)
105 if (num_phys_regions >= ARRAY_SIZE(phys_regions)) {
106 printk("phys_region overflow\n");
109 phys_regions[num_phys_regions].base = base;
110 phys_regions[num_phys_regions].size = size;
114 txboard_find_free_phys_region(unsigned long begin, unsigned long end,
120 for (base = begin / size * size; base < end; base += size) {
121 for (i = 0; i < num_phys_regions; i++) {
122 if (phys_regions[i].size &&
123 base <= phys_regions[i].base + (phys_regions[i].size - 1) &&
124 base + (size - 1) >= phys_regions[i].base)
127 if (i == num_phys_regions)
133 txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end,
136 unsigned long sz, base;
137 for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) {
138 base = txboard_find_free_phys_region(begin, end, sz);
147 txboard_request_phys_region_range(unsigned long begin, unsigned long end,
151 base = txboard_find_free_phys_region(begin, end, size);
153 txboard_add_phys_region(base, size);
157 txboard_request_phys_region(unsigned long size)
160 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
161 base = txboard_find_free_phys_region(begin, end, size);
163 txboard_add_phys_region(base, size);
167 txboard_request_phys_region_shrink(unsigned long *size)
170 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
171 base = txboard_find_free_phys_region_shrink(begin, end, size);
173 txboard_add_phys_region(base, *size);
179 tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr,
180 struct pci_controller *channel,
181 unsigned long pci_io_base,
186 /* Disable All Initiator Space */
187 pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)|
188 TX4938_PCIC_PCICCFG_G2PMEN(1)|
189 TX4938_PCIC_PCICCFG_G2PMEN(2)|
190 TX4938_PCIC_PCICCFG_G2PIOEN);
192 /* GB->PCI mappings */
193 pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4;
194 pcicptr->g2piogbase = pci_io_base |
196 TX4938_PCIC_G2PIOGBASE_ECHG
198 TX4938_PCIC_G2PIOGBASE_BSDIS
201 pcicptr->g2piopbase = 0;
202 for (i = 0; i < 3; i++) {
203 pcicptr->g2pmmask[i] = 0;
204 pcicptr->g2pmgbase[i] = 0;
205 pcicptr->g2pmpbase[i] = 0;
207 if (channel->mem_resource->end) {
208 pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4;
209 pcicptr->g2pmgbase[0] = channel->mem_resource->start |
211 TX4938_PCIC_G2PMnGBASE_ECHG
213 TX4938_PCIC_G2PMnGBASE_BSDIS
216 pcicptr->g2pmpbase[0] = channel->mem_resource->start;
218 /* PCI->GB mappings (I/O 256B) */
219 pcicptr->p2giopbase = 0; /* 256B */
220 pcicptr->p2giogbase = 0;
221 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
222 pcicptr->p2gm0plbase = 0;
223 pcicptr->p2gm0pubase = 0;
224 pcicptr->p2gmgbase[0] = 0 |
225 TX4938_PCIC_P2GMnGBASE_TMEMEN |
227 TX4938_PCIC_P2GMnGBASE_TECHG
229 TX4938_PCIC_P2GMnGBASE_TBSDIS
232 /* PCI->GB mappings (MEM 16MB) */
233 pcicptr->p2gm1plbase = 0xffffffff;
234 pcicptr->p2gm1pubase = 0xffffffff;
235 pcicptr->p2gmgbase[1] = 0;
236 /* PCI->GB mappings (MEM 1MB) */
237 pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */
238 pcicptr->p2gmgbase[2] = 0;
240 pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK;
241 /* Enable Initiator Memory Space */
242 if (channel->mem_resource->end)
243 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0);
244 /* Enable Initiator I/O Space */
245 if (channel->io_resource->end)
246 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN;
247 /* Enable Initiator Config */
249 TX4938_PCIC_PCICCFG_ICAEN |
250 TX4938_PCIC_PCICCFG_TCAR;
252 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
253 pcicptr->pcicfg1 = 0;
255 pcicptr->g2ptocnt &= ~0xffff;
257 if (tx4938_pcic_trdyto >= 0) {
258 pcicptr->g2ptocnt &= ~0xff;
259 pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff);
262 if (tx4938_pcic_retryto >= 0) {
263 pcicptr->g2ptocnt &= ~0xff00;
264 pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00);
267 /* Clear All Local Bus Status */
268 pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL;
269 /* Enable All Local Bus Interrupts */
270 pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL;
271 /* Clear All Initiator Status */
272 pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL;
273 /* Enable All Initiator Interrupts */
274 pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL;
275 /* Clear All PCI Status Error */
277 (pcicptr->pcistatus & 0x0000ffff) |
278 (TX4938_PCIC_PCISTATUS_ALL << 16);
279 /* Enable All PCI Status Error Interrupts */
280 pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL;
283 /* Reset Bus Arbiter */
284 pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA;
286 /* Enable Bus Arbiter */
287 pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN;
290 /* PCIC Int => IRC IRQ16 */
292 (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC;
294 pcicptr->pcistatus = PCI_COMMAND_MASTER |
296 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
300 tx4938_report_pciclk(void)
302 unsigned long pcode = TX4938_REV_PCODE();
304 printk("TX%lx PCIC --%s PCICLK:",
306 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : "");
307 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
309 switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) {
310 case TX4938_CCFG_PCIDIVMODE_4:
311 pciclk = txx9_cpu_clock / 4; break;
312 case TX4938_CCFG_PCIDIVMODE_4_5:
313 pciclk = txx9_cpu_clock * 2 / 9; break;
314 case TX4938_CCFG_PCIDIVMODE_5:
315 pciclk = txx9_cpu_clock / 5; break;
316 case TX4938_CCFG_PCIDIVMODE_5_5:
317 pciclk = txx9_cpu_clock * 2 / 11; break;
318 case TX4938_CCFG_PCIDIVMODE_8:
319 pciclk = txx9_cpu_clock / 8; break;
320 case TX4938_CCFG_PCIDIVMODE_9:
321 pciclk = txx9_cpu_clock / 9; break;
322 case TX4938_CCFG_PCIDIVMODE_10:
323 pciclk = txx9_cpu_clock / 10; break;
324 case TX4938_CCFG_PCIDIVMODE_11:
325 pciclk = txx9_cpu_clock / 11; break;
327 printk("Internal(%dMHz)", pciclk / 1000000);
336 void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr)
338 pcicptrs[ch] = pcicptr;
341 struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch)
346 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
347 int top_bus, int busnr, int devfn)
349 static struct pci_dev dev;
350 static struct pci_bus bus;
352 dev.sysdata = bus.sysdata = hose;
355 bus.ops = hose->pci_ops;
362 #define EARLY_PCI_OP(rw, size, type) \
363 static int early_##rw##_config_##size(struct pci_controller *hose, \
364 int top_bus, int bus, int devfn, int offset, type value) \
366 return pci_##rw##_config_##size( \
367 fake_pci_dev(hose, top_bus, bus, devfn), \
371 EARLY_PCI_OP(read, word, u16 *)
373 int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus)
378 int devfn_stop = 0xff;
382 printk("PCI: Checking 66MHz capabilities...\n");
384 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
385 if (early_read_config_word(hose, top_bus, current_bus,
386 pci_devfn, PCI_VENDOR_ID,
387 &vid) != PCIBIOS_SUCCESSFUL)
390 if (vid == 0xffff) continue;
392 /* check 66MHz capability */
396 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
398 if (!(stat & PCI_STATUS_66MHZ)) {
399 printk(KERN_DEBUG "PCI: %02x:%02x not 66MHz capable.\n",
400 current_bus, pci_devfn);
410 tx4938_pciclk66_setup(void)
415 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66;
416 /* Double PCICLK (if possible) */
417 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
418 unsigned int pcidivmode =
419 tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK;
420 switch (pcidivmode) {
421 case TX4938_CCFG_PCIDIVMODE_8:
422 case TX4938_CCFG_PCIDIVMODE_4:
423 pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
424 pciclk = txx9_cpu_clock / 4;
426 case TX4938_CCFG_PCIDIVMODE_9:
427 case TX4938_CCFG_PCIDIVMODE_4_5:
428 pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
429 pciclk = txx9_cpu_clock * 2 / 9;
431 case TX4938_CCFG_PCIDIVMODE_10:
432 case TX4938_CCFG_PCIDIVMODE_5:
433 pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
434 pciclk = txx9_cpu_clock / 5;
436 case TX4938_CCFG_PCIDIVMODE_11:
437 case TX4938_CCFG_PCIDIVMODE_5_5:
439 pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
440 pciclk = txx9_cpu_clock * 2 / 11;
443 tx4938_ccfgptr->ccfg =
444 (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK)
446 printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
447 (unsigned long)tx4938_ccfgptr->ccfg);
454 extern struct pci_controller tx4938_pci_controller[];
455 static int __init tx4938_pcibios_init(void)
457 unsigned long mem_base[2];
458 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */
459 unsigned long io_base[2];
460 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */
461 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */
462 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
464 PCIBIOS_MIN_IO = 0x00001000UL;
466 mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]);
467 io_base[0] = txboard_request_phys_region_shrink(&io_size[0]);
469 printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
470 (unsigned short)(tx4938_pcicptr->pciid >> 16),
471 (unsigned short)(tx4938_pcicptr->pciid & 0xffff),
472 (unsigned short)(tx4938_pcicptr->pciccrev & 0xff),
473 extarb ? "External" : "Internal");
476 tx4938_pci_controller[0].io_resource->start = io_base[0];
477 tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1;
478 tx4938_pci_controller[0].mem_resource->start = mem_base[0];
479 tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1;
481 set_tx4938_pcicptr(0, tx4938_pcicptr);
483 register_pci_controller(&tx4938_pci_controller[0]);
485 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) {
486 printk("TX4938_CCFG_PCI66 already configured\n");
487 txboard_pci66_mode = -1; /* already configured */
491 *rbtx4938_pcireset_ptr = 0;
493 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
494 if (txboard_pci66_mode > 0)
495 tx4938_pciclk66_setup();
497 /* clear PCIC reset */
498 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
499 *rbtx4938_pcireset_ptr = 1;
501 tx4938_report_pcic_status1(tx4938_pcicptr);
503 tx4938_report_pciclk();
504 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
505 if (txboard_pci66_mode == 0 &&
506 txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) {
508 *rbtx4938_pcireset_ptr = 0;
510 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
511 tx4938_pciclk66_setup();
513 /* clear PCIC reset */
514 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
515 *rbtx4938_pcireset_ptr = 1;
517 /* Reinitialize PCIC */
518 tx4938_report_pciclk();
519 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
522 mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]);
523 io_base[1] = txboard_request_phys_region_shrink(&io_size[1]);
525 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST;
526 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
527 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD))
528 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66;
530 tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66;
532 /* clear PCIC1 reset */
533 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
534 tx4938_report_pcic_status1(tx4938_pcic1ptr);
536 printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x",
537 (unsigned short)(tx4938_pcic1ptr->pciid >> 16),
538 (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff),
539 (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff));
540 printk("%s PCICLK:%dMHz\n",
541 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "",
543 ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) /
546 /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */
547 tx4938_pci_controller[1].io_resource->start =
548 io_base[1] - io_base[0];
549 tx4938_pci_controller[1].io_resource->end =
550 io_base[1] - io_base[0] + io_size[1] - 1;
551 tx4938_pci_controller[1].mem_resource->start = mem_base[1];
552 tx4938_pci_controller[1].mem_resource->end =
553 mem_base[1] + mem_size[1] - 1;
554 set_tx4938_pcicptr(1, tx4938_pcic1ptr);
556 register_pci_controller(&tx4938_pci_controller[1]);
558 tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb);
560 /* map ioport 0 to PCI I/O space address 0 */
561 set_io_port_base(KSEG1 + io_base[0]);
566 arch_initcall(tx4938_pcibios_init);
568 #endif /* CONFIG_PCI */
572 /* chip select for SPI devices */
573 #define SEEPROM1_CS 7 /* PIO7 */
574 #define SEEPROM2_CS 0 /* IOC */
575 #define SEEPROM3_CS 1 /* IOC */
576 #define SRTC_CS 2 /* IOC */
579 static int __init rbtx4938_ethaddr_init(void)
581 unsigned char dat[17];
585 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
586 if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) {
587 printk(KERN_ERR "seeprom: read error.\n");
590 if (strcmp(dat, "MAC") != 0)
591 printk(KERN_WARNING "seeprom: bad signature.\n");
592 for (i = 0, sum = 0; i < sizeof(dat); i++)
595 printk(KERN_WARNING "seeprom: bad checksum.\n");
597 for (i = 0; i < 2; i++) {
599 TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0);
600 struct platform_device *pdev;
601 if (!(tx4938_ccfgptr->pcfg &
602 (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL)))
604 pdev = platform_device_alloc("tc35815-mac", id);
606 platform_device_add_data(pdev, &dat[4 + 6 * i], 6) ||
607 platform_device_add(pdev))
608 platform_device_put(pdev);
612 device_initcall(rbtx4938_ethaddr_init);
613 #endif /* CONFIG_PCI */
615 static void __init rbtx4938_spi_setup(void)
618 tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL;
621 static struct resource rbtx4938_fpga_resource;
623 static char pcode_str[8];
624 static struct resource tx4938_reg_resource = {
625 .start = TX4938_REG_BASE,
626 .end = TX4938_REG_BASE + TX4938_REG_SIZE,
628 .flags = IORESOURCE_MEM
631 void __init tx4938_board_setup(void)
634 unsigned long divmode;
636 unsigned long pcode = TX4938_REV_PCODE();
638 ioport_resource.start = 0x1000;
639 ioport_resource.end = 0xffffffff;
640 iomem_resource.start = 0x1000;
641 iomem_resource.end = 0xffffffff; /* expand to 4GB */
643 sprintf(pcode_str, "TX%lx", pcode);
644 /* SDRAMC,EBUSC are configured by PROM */
645 for (i = 0; i < 8; i++) {
646 if (!(tx4938_ebuscptr->cr[i] & 0x8))
647 continue; /* disabled */
648 rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i);
649 txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i));
653 if (txx9_master_clock) {
654 /* calculate gbus_clock and cpu_clock_freq from master_clock */
655 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
657 case TX4938_CCFG_DIVMODE_8:
658 case TX4938_CCFG_DIVMODE_10:
659 case TX4938_CCFG_DIVMODE_12:
660 case TX4938_CCFG_DIVMODE_16:
661 case TX4938_CCFG_DIVMODE_18:
662 txx9_gbus_clock = txx9_master_clock * 4; break;
664 txx9_gbus_clock = txx9_master_clock;
667 case TX4938_CCFG_DIVMODE_2:
668 case TX4938_CCFG_DIVMODE_8:
669 cpuclk = txx9_gbus_clock * 2; break;
670 case TX4938_CCFG_DIVMODE_2_5:
671 case TX4938_CCFG_DIVMODE_10:
672 cpuclk = txx9_gbus_clock * 5 / 2; break;
673 case TX4938_CCFG_DIVMODE_3:
674 case TX4938_CCFG_DIVMODE_12:
675 cpuclk = txx9_gbus_clock * 3; break;
676 case TX4938_CCFG_DIVMODE_4:
677 case TX4938_CCFG_DIVMODE_16:
678 cpuclk = txx9_gbus_clock * 4; break;
679 case TX4938_CCFG_DIVMODE_4_5:
680 case TX4938_CCFG_DIVMODE_18:
681 cpuclk = txx9_gbus_clock * 9 / 2; break;
683 txx9_cpu_clock = cpuclk;
685 if (txx9_cpu_clock == 0) {
686 txx9_cpu_clock = 300000000; /* 300MHz */
688 /* calculate gbus_clock and master_clock from cpu_clock_freq */
689 cpuclk = txx9_cpu_clock;
690 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
692 case TX4938_CCFG_DIVMODE_2:
693 case TX4938_CCFG_DIVMODE_8:
694 txx9_gbus_clock = cpuclk / 2; break;
695 case TX4938_CCFG_DIVMODE_2_5:
696 case TX4938_CCFG_DIVMODE_10:
697 txx9_gbus_clock = cpuclk * 2 / 5; break;
698 case TX4938_CCFG_DIVMODE_3:
699 case TX4938_CCFG_DIVMODE_12:
700 txx9_gbus_clock = cpuclk / 3; break;
701 case TX4938_CCFG_DIVMODE_4:
702 case TX4938_CCFG_DIVMODE_16:
703 txx9_gbus_clock = cpuclk / 4; break;
704 case TX4938_CCFG_DIVMODE_4_5:
705 case TX4938_CCFG_DIVMODE_18:
706 txx9_gbus_clock = cpuclk * 2 / 9; break;
709 case TX4938_CCFG_DIVMODE_8:
710 case TX4938_CCFG_DIVMODE_10:
711 case TX4938_CCFG_DIVMODE_12:
712 case TX4938_CCFG_DIVMODE_16:
713 case TX4938_CCFG_DIVMODE_18:
714 txx9_master_clock = txx9_gbus_clock / 4; break;
716 txx9_master_clock = txx9_gbus_clock;
719 /* change default value to udelay/mdelay take reasonable time */
720 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
723 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
724 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW;
725 /* do reset on watchdog */
726 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WR;
727 /* clear PCIC1 reset */
728 if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST)
729 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
731 /* enable Timeout BusError */
732 if (tx4938_ccfg_toeon)
733 tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE;
736 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL;
738 /* Use external clock for external arbiter */
739 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB))
740 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL;
742 printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n",
744 cpuclk / 1000000, txx9_master_clock / 1000000,
745 (unsigned long)tx4938_ccfgptr->crir,
746 tx4938_ccfgptr->ccfg,
747 tx4938_ccfgptr->pcfg);
749 printk("%s SDRAMC --", pcode_str);
750 for (i = 0; i < 4; i++) {
751 unsigned long long cr = tx4938_sdramcptr->cr[i];
752 unsigned long ram_base, ram_size;
753 if (!((unsigned long)cr & 0x00000400))
754 continue; /* disabled */
755 ram_base = (unsigned long)(cr >> 49) << 21;
756 ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
757 if (ram_base >= 0x20000000)
758 continue; /* high memory (ignore) */
759 printk(" CR%d:%016Lx", i, cr);
760 txboard_add_phys_region(ram_base, ram_size);
762 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr);
765 if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) {
766 unsigned int size = 0x800;
768 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1);
769 txboard_add_phys_region(base, size);
773 for (i = 0; i < TX4938_NR_TMR; i++)
774 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
777 TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
778 TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN);
781 __raw_writel(0, &tx4938_pioptr->maskcpu);
782 __raw_writel(0, &tx4938_pioptr->maskext);
784 /* TX4938 internal registers */
785 if (request_resource(&iomem_resource, &tx4938_reg_resource))
786 printk("request resource for internal registers failed\n");
790 static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr)
792 unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16);
793 unsigned long g2pstatus = pcicptr->g2pstatus;
794 unsigned long pcicstatus = pcicptr->pcicstatus;
799 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
800 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
801 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
802 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
803 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
804 { PCI_STATUS_PARITY, "MasterParityError" },
806 { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" },
807 { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" },
808 }, pcicstat_tbl[] = {
809 { TX4938_PCIC_PCICSTATUS_PME, "PME" },
810 { TX4938_PCIC_PCICSTATUS_TLB, "TLB" },
811 { TX4938_PCIC_PCICSTATUS_NIB, "NIB" },
812 { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" },
813 { TX4938_PCIC_PCICSTATUS_PERR, "PERR" },
814 { TX4938_PCIC_PCICSTATUS_SERR, "SERR" },
815 { TX4938_PCIC_PCICSTATUS_GBE, "GBE" },
816 { TX4938_PCIC_PCICSTATUS_IWB, "IWB" },
820 printk("pcistat:%04x(", pcistatus);
821 for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
822 if (pcistatus & pcistat_tbl[i].flag)
823 printk("%s ", pcistat_tbl[i].str);
824 printk("), g2pstatus:%08lx(", g2pstatus);
825 for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
826 if (g2pstatus & g2pstat_tbl[i].flag)
827 printk("%s ", g2pstat_tbl[i].str);
828 printk("), pcicstatus:%08lx(", pcicstatus);
829 for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
830 if (pcicstatus & pcicstat_tbl[i].flag)
831 printk("%s ", pcicstat_tbl[i].str);
835 void tx4938_report_pcic_status(void)
838 struct tx4938_pcic_reg *pcicptr;
839 for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++)
840 tx4938_report_pcic_status1(pcicptr);
843 #endif /* CONFIG_PCI */
845 void __init plat_time_init(void)
847 mips_hpt_frequency = txx9_cpu_clock / 2;
848 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS)
849 txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL,
850 TXX9_IRQ_BASE + TX4938_IR_TMR(0),
851 txx9_gbus_clock / 2);
854 void __init plat_mem_setup(void)
856 unsigned long long pcfg;
859 iomem_resource.end = 0xffffffff; /* 4GB */
861 if (txx9_master_clock == 0)
862 txx9_master_clock = 25000000; /* 25MHz */
863 tx4938_board_setup();
864 /* setup serial stuff */
865 TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
866 TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
869 set_io_port_base(RBTX4938_ETHER_BASE);
872 #ifdef CONFIG_SERIAL_TXX9
874 extern int early_serial_txx9_setup(struct uart_port *port);
876 struct uart_port req;
877 for(i = 0; i < 2; i++) {
878 memset(&req, 0, sizeof(req));
880 req.iotype = UPIO_MEM;
881 req.membase = (char *)(0xff1ff300 + i * 0x100);
882 req.mapbase = 0xff1ff300 + i * 0x100;
883 req.irq = RBTX4938_IRQ_IRC_SIO(i);
884 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
885 req.uartclk = 50000000;
886 early_serial_txx9_setup(&req);
889 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
890 argptr = prom_getcmdline();
891 if (strstr(argptr, "console=") == NULL) {
892 strcat(argptr, " console=ttyS0,38400");
897 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
898 printk("PIOSEL: disabling both ata and nand selection\n");
900 tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
903 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
904 printk("PIOSEL: enabling nand selection\n");
905 tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL;
906 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL;
909 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
910 printk("PIOSEL: enabling ata selection\n");
911 tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL;
912 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL;
916 argptr = prom_getcmdline();
917 if (strstr(argptr, "ip=") == NULL) {
918 strcat(argptr, " ip=any");
925 conswitchp = &dummy_con;
929 rbtx4938_spi_setup();
930 pcfg = tx4938_ccfgptr->pcfg; /* updated */
932 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
933 TX4938_PCFG_ATA_SEL) {
934 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x04;
936 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
937 TX4938_PCFG_NDF_SEL) {
938 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x08;
941 *rbtx4938_piosel_ptr &= ~(0x08 | 0x04);
944 rbtx4938_fpga_resource.name = "FPGA Registers";
945 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
946 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
947 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
948 if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))
949 printk("request resource for fpga failed\n");
951 /* disable all OnBoard I/O interrupts */
952 *rbtx4938_imask_ptr = 0;
954 _machine_restart = rbtx4938_machine_restart;
955 _machine_halt = rbtx4938_machine_halt;
956 pm_power_off = rbtx4938_machine_power_off;
958 *rbtx4938_led_ptr = 0xff;
959 printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr);
960 printk(" DIPSW:%02x,%02x\n",
961 *rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr);
964 static int __init rbtx4938_ne_init(void)
966 struct resource res[] = {
968 .start = RBTX4938_RTL_8019_BASE,
969 .end = RBTX4938_RTL_8019_BASE + 0x20 - 1,
970 .flags = IORESOURCE_IO,
972 .start = RBTX4938_RTL_8019_IRQ,
973 .flags = IORESOURCE_IRQ,
976 struct platform_device *dev =
977 platform_device_register_simple("ne", -1,
978 res, ARRAY_SIZE(res));
979 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
981 device_initcall(rbtx4938_ne_init);
985 int gpio_to_irq(unsigned gpio)
990 int irq_to_gpio(unsigned irq)
995 static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
997 static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
1001 unsigned long flags;
1002 spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
1003 val = *rbtx4938_spics_ptr;
1007 val &= ~(1 << offset);
1008 *rbtx4938_spics_ptr = val;
1010 spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
1013 static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip,
1014 unsigned int offset, int value)
1016 rbtx4938_spi_gpio_set(chip, offset, value);
1020 static struct gpio_chip rbtx4938_spi_gpio_chip = {
1021 .set = rbtx4938_spi_gpio_set,
1022 .direction_output = rbtx4938_spi_gpio_dir_out,
1023 .label = "RBTX4938-SPICS",
1030 static void __init txx9_spi_init(unsigned long base, int irq)
1032 struct resource res[] = {
1035 .end = base + 0x20 - 1,
1036 .flags = IORESOURCE_MEM,
1037 .parent = &tx4938_reg_resource,
1040 .flags = IORESOURCE_IRQ,
1043 platform_device_register_simple("spi_txx9", 0,
1044 res, ARRAY_SIZE(res));
1047 static int __init rbtx4938_spi_init(void)
1049 struct spi_board_info srtc_info = {
1050 .modalias = "rtc-rs5c348",
1051 .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
1053 .chip_select = 16 + SRTC_CS,
1054 /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */
1055 .mode = SPI_MODE_1 | SPI_CS_HIGH,
1057 spi_register_board_info(&srtc_info, 1);
1058 spi_eeprom_register(SEEPROM1_CS);
1059 spi_eeprom_register(16 + SEEPROM2_CS);
1060 spi_eeprom_register(16 + SEEPROM3_CS);
1061 gpio_request(16 + SRTC_CS, "rtc-rs5c348");
1062 gpio_direction_output(16 + SRTC_CS, 0);
1063 gpio_request(SEEPROM1_CS, "seeprom1");
1064 gpio_direction_output(SEEPROM1_CS, 1);
1065 gpio_request(16 + SEEPROM2_CS, "seeprom2");
1066 gpio_direction_output(16 + SEEPROM2_CS, 1);
1067 gpio_request(16 + SEEPROM3_CS, "seeprom3");
1068 gpio_direction_output(16 + SEEPROM3_CS, 1);
1069 txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI);
1073 static int __init rbtx4938_arch_init(void)
1075 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16);
1076 gpiochip_add(&rbtx4938_spi_gpio_chip);
1077 return rbtx4938_spi_init();
1079 arch_initcall(rbtx4938_arch_init);
1081 /* Watchdog support */
1083 static int __init txx9_wdt_init(unsigned long base)
1085 struct resource res = {
1087 .end = base + 0x100 - 1,
1088 .flags = IORESOURCE_MEM,
1089 .parent = &tx4938_reg_resource,
1091 struct platform_device *dev =
1092 platform_device_register_simple("txx9wdt", -1, &res, 1);
1093 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
1096 static int __init rbtx4938_wdt_init(void)
1098 return txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL);
1100 device_initcall(rbtx4938_wdt_init);
1102 /* Minimum CLK support */
1104 struct clk *clk_get(struct device *dev, const char *id)
1106 if (!strcmp(id, "spi-baseclk"))
1107 return (struct clk *)(txx9_gbus_clock / 2 / 4);
1108 if (!strcmp(id, "imbus_clk"))
1109 return (struct clk *)(txx9_gbus_clock / 2);
1110 return ERR_PTR(-ENOENT);
1112 EXPORT_SYMBOL(clk_get);
1114 int clk_enable(struct clk *clk)
1118 EXPORT_SYMBOL(clk_enable);
1120 void clk_disable(struct clk *clk)
1123 EXPORT_SYMBOL(clk_disable);
1125 unsigned long clk_get_rate(struct clk *clk)
1127 return (unsigned long)clk;
1129 EXPORT_SYMBOL(clk_get_rate);
1131 void clk_put(struct clk *clk)
1134 EXPORT_SYMBOL(clk_put);