2 * linux/arch/mips/tx4938/toshiba_rbtx4938/irq.c
4 * Toshiba RBTX4938 specific interrupt handlers
5 * Copyright (C) 2000-2001 Toshiba Corporation
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
18 16 TX4938-CP0/00 Software 0
19 17 TX4938-CP0/01 Software 1
20 18 TX4938-CP0/02 Cascade TX4938-CP0
21 19 TX4938-CP0/03 Multiplexed -- do not use
22 20 TX4938-CP0/04 Multiplexed -- do not use
23 21 TX4938-CP0/05 Multiplexed -- do not use
24 22 TX4938-CP0/06 Multiplexed -- do not use
25 23 TX4938-CP0/07 CPU TIMER
29 26 TX4938-PIC/02 Cascade RBTX4938-IOC
30 27 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet
32 29 TX4938-PIC/05 TX4938 ETH1
33 30 TX4938-PIC/06 TX4938 ETH0
35 32 TX4938-PIC/08 TX4938 SIO 0
36 33 TX4938-PIC/09 TX4938 SIO 1
37 34 TX4938-PIC/10 TX4938 DMA0
38 35 TX4938-PIC/11 TX4938 DMA1
39 36 TX4938-PIC/12 TX4938 DMA2
40 37 TX4938-PIC/13 TX4938 DMA3
43 40 TX4938-PIC/16 TX4938 PCIC
44 41 TX4938-PIC/17 TX4938 TMR0
45 42 TX4938-PIC/18 TX4938 TMR1
46 43 TX4938-PIC/19 TX4938 TMR2
49 46 TX4938-PIC/22 TX4938 PCIERR
58 55 TX4938-PIC/31 TX4938 SPI
60 56 RBTX4938-IOC/00 PCI-D
61 57 RBTX4938-IOC/01 PCI-C
62 58 RBTX4938-IOC/02 PCI-B
63 59 RBTX4938-IOC/03 PCI-A
64 60 RBTX4938-IOC/04 RTC
65 61 RBTX4938-IOC/05 ATA
66 62 RBTX4938-IOC/06 MODEM
67 63 RBTX4938-IOC/07 SWINT
69 #include <linux/init.h>
70 #include <linux/interrupt.h>
71 #include <asm/tx4938/rbtx4938.h>
73 static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
74 static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
76 #define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
77 static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
78 .name = TOSHIBA_RBTX4938_IOC_NAME,
79 .ack = toshiba_rbtx4938_irq_ioc_disable,
80 .mask = toshiba_rbtx4938_irq_ioc_disable,
81 .mask_ack = toshiba_rbtx4938_irq_ioc_disable,
82 .unmask = toshiba_rbtx4938_irq_ioc_enable,
86 toshiba_rbtx4938_irq_nested(int sw_irq)
90 level3 = readb(rbtx4938_imstat_addr);
92 /* must use fls so onboard ATA has priority */
93 sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1;
98 static struct irqaction toshiba_rbtx4938_irq_ioc_action = {
101 .mask = CPU_MASK_NONE,
102 .name = TOSHIBA_RBTX4938_IOC_NAME,
105 /**********************************************************************************/
106 /* Functions for ioc */
107 /**********************************************************************************/
109 toshiba_rbtx4938_irq_ioc_init(void)
113 for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG;
114 i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++)
115 set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
118 setup_irq(RBTX4938_IRQ_IOCINT,
119 &toshiba_rbtx4938_irq_ioc_action);
123 toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
127 v = readb(rbtx4938_imask_addr);
128 v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
129 writeb(v, rbtx4938_imask_addr);
134 toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
138 v = readb(rbtx4938_imask_addr);
139 v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
140 writeb(v, rbtx4938_imask_addr);
144 void __init arch_init_irq(void)
146 extern void tx4938_irq_init(void);
148 /* Now, interrupt control disabled, */
149 /* all IRC interrupts are masked, */
150 /* all IRC interrupt mode are Low Active. */
152 /* mask all IOC interrupts */
153 writeb(0, rbtx4938_imask_addr);
155 /* clear SoftInt interrupts */
156 writeb(0, rbtx4938_softint_addr);
158 toshiba_rbtx4938_irq_ioc_init();
159 /* Onboard 10M Ether: High Active */
160 set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);