2 * Toshiba rbtx4927 specific setup
4 * Author: MontaVista Software, Inc.
7 * Copyright 2001-2002 MontaVista Software Inc.
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
10 * Copyright (C) 2000 RidgeRun, Inc.
11 * Author: RidgeRun, Inc.
12 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
14 * Copyright 2001 MontaVista Software Inc.
15 * Author: jsun@mvista.com or jsun@junsun.net
17 * Copyright 2002 MontaVista Software Inc.
18 * Author: Michael Pruznick, michael_pruznick@mvista.com
20 * Copyright (C) 2000-2001 Toshiba Corporation
22 * Copyright (C) 2004 MontaVista Software Inc.
23 * Author: Manish Lachwani, mlachwani@mvista.com
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms of the GNU General Public License as published by the
27 * Free Software Foundation; either version 2 of the License, or (at your
28 * option) any later version.
30 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
31 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
35 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
36 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
38 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
39 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * You should have received a copy of the GNU General Public License along
42 * with this program; if not, write to the Free Software Foundation, Inc.,
43 * 675 Mass Ave, Cambridge, MA 02139, USA.
45 #include <linux/init.h>
46 #include <linux/kernel.h>
47 #include <linux/types.h>
49 #include <linux/swap.h>
50 #include <linux/ioport.h>
51 #include <linux/sched.h>
52 #include <linux/interrupt.h>
53 #include <linux/pci.h>
54 #include <linux/timex.h>
56 #include <linux/platform_device.h>
58 #include <asm/bootinfo.h>
62 #include <asm/irq_regs.h>
63 #include <asm/processor.h>
64 #include <asm/reboot.h>
66 #include <linux/bootmem.h>
67 #include <linux/blkdev.h>
68 #ifdef CONFIG_TOSHIBA_FPCIB0
69 #include <asm/tx4927/smsc_fdc37m81x.h>
71 #include <asm/tx4927/toshiba_rbtx4927.h>
73 #include <asm/tx4927/tx4927_pci.h>
75 #ifdef CONFIG_BLK_DEV_IDEPCI
76 #include <linux/hdreg.h>
77 #include <linux/ide.h>
79 #ifdef CONFIG_SERIAL_TXX9
80 #include <linux/tty.h>
81 #include <linux/serial.h>
82 #include <linux/serial_core.h>
85 #undef TOSHIBA_RBTX4927_SETUP_DEBUG
87 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
88 #define TOSHIBA_RBTX4927_SETUP_NONE 0x00000000
90 #define TOSHIBA_RBTX4927_SETUP_INFO ( 1 << 0 )
91 #define TOSHIBA_RBTX4927_SETUP_WARN ( 1 << 1 )
92 #define TOSHIBA_RBTX4927_SETUP_EROR ( 1 << 2 )
94 #define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 )
95 #define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
96 #define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 )
97 #define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
98 #define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
99 #define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
100 #define TOSHIBA_RBTX4927_SETUP_PCI66 ( 1 << 10 )
102 #define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
105 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
106 static const u32 toshiba_rbtx4927_setup_debug_flag =
107 (TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO |
108 TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR |
109 TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP |
110 | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
111 TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66);
114 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
115 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \
116 if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \
119 sprintf( tmp, str ); \
120 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
123 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag, str...)
126 /* These functions are used for rebooting or halting the machine*/
127 extern void toshiba_rbtx4927_restart(char *command);
128 extern void toshiba_rbtx4927_halt(void);
129 extern void toshiba_rbtx4927_power_off(void);
131 int tx4927_using_backplane = 0;
133 extern void gt64120_time_init(void);
134 extern void toshiba_rbtx4927_irq_setup(void);
136 char *prom_getcmdline(void);
139 #undef TX4927_SUPPORT_COMMAND_IO
140 #undef TX4927_SUPPORT_PCI_66
141 int tx4927_cpu_clock = 100000000; /* 100MHz */
142 unsigned long mips_pci_io_base;
143 unsigned long mips_pci_io_size;
144 unsigned long mips_pci_mem_base;
145 unsigned long mips_pci_mem_size;
146 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
147 unsigned long mips_pci_io_pciaddr = 0;
148 unsigned long mips_memory_upper;
149 static int tx4927_ccfg_toeon = 1;
150 static int tx4927_pcic_trdyto = 0; /* default: disabled */
151 unsigned long tx4927_ce_base[8];
152 void tx4927_reset_pci_pcic(void);
153 int tx4927_pci66 = 0; /* 0:auto */
156 char *toshiba_name = "";
159 extern struct pci_controller tx4927_controller;
161 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
162 int top_bus, int busnr, int devfn)
164 static struct pci_dev dev;
165 static struct pci_bus bus;
167 dev.sysdata = (void *)hose;
170 bus.ops = hose->pci_ops;
177 #define EARLY_PCI_OP(rw, size, type) \
178 static int early_##rw##_config_##size(struct pci_controller *hose, \
179 int top_bus, int bus, int devfn, int offset, type value) \
181 return pci_##rw##_config_##size( \
182 fake_pci_dev(hose, top_bus, bus, devfn), \
186 EARLY_PCI_OP(read, byte, u8 *)
187 EARLY_PCI_OP(read, dword, u32 *)
188 EARLY_PCI_OP(write, byte, u8)
189 EARLY_PCI_OP(write, dword, u32)
191 static int __init tx4927_pcibios_init(void)
196 int devfn_stop = 0xff;
197 int busno = 0; /* One bus on the Toshiba */
198 struct pci_controller *hose = &tx4927_controller;
200 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
203 for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
204 early_read_config_dword(hose, busno, busno, pci_devfn,
207 if (id == 0xffffffff) {
211 if (id == 0x94601055) {
215 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
216 char *s = " sb/isa --";
219 TOSHIBA_RBTX4927_SETUP_DPRINTK
220 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
223 early_read_config_byte(hose, busno, busno,
224 pci_devfn, 0x64, &v08_64);
225 early_read_config_dword(hose, busno, busno,
226 pci_devfn, 0xb0, &v32_b0);
227 early_read_config_byte(hose, busno, busno,
228 pci_devfn, 0xe1, &v08_e1);
230 TOSHIBA_RBTX4927_SETUP_DPRINTK
231 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
232 ":%s beg 0x64 = 0x%02x\n", s, v08_64);
233 TOSHIBA_RBTX4927_SETUP_DPRINTK
234 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
235 ":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
236 TOSHIBA_RBTX4927_SETUP_DPRINTK
237 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
238 ":%s beg 0xe1 = 0x%02x\n", s, v08_e1);
240 /* serial irq control */
244 v32_b0 |= 0x00010000;
246 /* ide irq on isa14 */
250 TOSHIBA_RBTX4927_SETUP_DPRINTK
251 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
252 ":%s mid 0x64 = 0x%02x\n", s, v08_64);
253 TOSHIBA_RBTX4927_SETUP_DPRINTK
254 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
255 ":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
256 TOSHIBA_RBTX4927_SETUP_DPRINTK
257 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
258 ":%s mid 0xe1 = 0x%02x\n", s, v08_e1);
260 early_write_config_byte(hose, busno, busno,
261 pci_devfn, 0x64, v08_64);
262 early_write_config_dword(hose, busno, busno,
263 pci_devfn, 0xb0, v32_b0);
264 early_write_config_byte(hose, busno, busno,
265 pci_devfn, 0xe1, v08_e1);
267 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
269 early_read_config_byte(hose, busno, busno,
272 early_read_config_dword(hose, busno, busno,
275 early_read_config_byte(hose, busno, busno,
279 TOSHIBA_RBTX4927_SETUP_DPRINTK
280 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
281 ":%s end 0x64 = 0x%02x\n", s, v08_64);
282 TOSHIBA_RBTX4927_SETUP_DPRINTK
283 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
284 ":%s end 0xb0 = 0x%02x\n", s, v32_b0);
285 TOSHIBA_RBTX4927_SETUP_DPRINTK
286 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
287 ":%s end 0xe1 = 0x%02x\n", s, v08_e1);
291 TOSHIBA_RBTX4927_SETUP_DPRINTK
292 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
296 if (id == 0x91301055) {
302 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
303 char *s = " sb/ide --";
306 TOSHIBA_RBTX4927_SETUP_DPRINTK
307 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
310 early_read_config_byte(hose, busno, busno,
311 pci_devfn, 0x04, &v08_04);
312 early_read_config_byte(hose, busno, busno,
313 pci_devfn, 0x09, &v08_09);
314 early_read_config_byte(hose, busno, busno,
315 pci_devfn, 0x41, &v08_41);
316 early_read_config_byte(hose, busno, busno,
317 pci_devfn, 0x43, &v08_43);
318 early_read_config_byte(hose, busno, busno,
319 pci_devfn, 0x5c, &v08_5c);
321 TOSHIBA_RBTX4927_SETUP_DPRINTK
322 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
323 ":%s beg 0x04 = 0x%02x\n", s, v08_04);
324 TOSHIBA_RBTX4927_SETUP_DPRINTK
325 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
326 ":%s beg 0x09 = 0x%02x\n", s, v08_09);
327 TOSHIBA_RBTX4927_SETUP_DPRINTK
328 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
329 ":%s beg 0x41 = 0x%02x\n", s, v08_41);
330 TOSHIBA_RBTX4927_SETUP_DPRINTK
331 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
332 ":%s beg 0x43 = 0x%02x\n", s, v08_43);
333 TOSHIBA_RBTX4927_SETUP_DPRINTK
334 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
335 ":%s beg 0x5c = 0x%02x\n", s, v08_5c);
337 /* enable ide master/io */
338 v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
340 /* enable ide native mode */
343 /* enable primary ide */
346 /* enable secondary ide */
350 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
352 * This line of code is intended to provide the user with a work
353 * around solution to the anomalies cited in SMSC's anomaly sheet
354 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
356 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
360 TOSHIBA_RBTX4927_SETUP_DPRINTK
361 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
362 ":%s mid 0x04 = 0x%02x\n", s, v08_04);
363 TOSHIBA_RBTX4927_SETUP_DPRINTK
364 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
365 ":%s mid 0x09 = 0x%02x\n", s, v08_09);
366 TOSHIBA_RBTX4927_SETUP_DPRINTK
367 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
368 ":%s mid 0x41 = 0x%02x\n", s, v08_41);
369 TOSHIBA_RBTX4927_SETUP_DPRINTK
370 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
371 ":%s mid 0x43 = 0x%02x\n", s, v08_43);
372 TOSHIBA_RBTX4927_SETUP_DPRINTK
373 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
374 ":%s mid 0x5c = 0x%02x\n", s, v08_5c);
376 early_write_config_byte(hose, busno, busno,
377 pci_devfn, 0x5c, v08_5c);
378 early_write_config_byte(hose, busno, busno,
379 pci_devfn, 0x04, v08_04);
380 early_write_config_byte(hose, busno, busno,
381 pci_devfn, 0x09, v08_09);
382 early_write_config_byte(hose, busno, busno,
383 pci_devfn, 0x41, v08_41);
384 early_write_config_byte(hose, busno, busno,
385 pci_devfn, 0x43, v08_43);
387 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
389 early_read_config_byte(hose, busno, busno,
392 early_read_config_byte(hose, busno, busno,
395 early_read_config_byte(hose, busno, busno,
398 early_read_config_byte(hose, busno, busno,
401 early_read_config_byte(hose, busno, busno,
405 TOSHIBA_RBTX4927_SETUP_DPRINTK
406 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
407 ":%s end 0x04 = 0x%02x\n", s, v08_04);
408 TOSHIBA_RBTX4927_SETUP_DPRINTK
409 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
410 ":%s end 0x09 = 0x%02x\n", s, v08_09);
411 TOSHIBA_RBTX4927_SETUP_DPRINTK
412 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
413 ":%s end 0x41 = 0x%02x\n", s, v08_41);
414 TOSHIBA_RBTX4927_SETUP_DPRINTK
415 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
416 ":%s end 0x43 = 0x%02x\n", s, v08_43);
417 TOSHIBA_RBTX4927_SETUP_DPRINTK
418 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
419 ":%s end 0x5c = 0x%02x\n", s, v08_5c);
423 TOSHIBA_RBTX4927_SETUP_DPRINTK
424 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
430 register_pci_controller(&tx4927_controller);
431 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
437 arch_initcall(tx4927_pcibios_init);
439 extern struct resource pci_io_resource;
440 extern struct resource pci_mem_resource;
442 void __init tx4927_pci_setup(void)
444 static int called = 0;
445 extern unsigned int tx4927_get_mem_size(void);
447 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");
449 mips_memory_upper = tx4927_get_mem_size() << 20;
450 mips_memory_upper += KSEG0;
451 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
452 "0x%08lx=mips_memory_upper\n",
454 mips_pci_io_base = TX4927_PCIIO;
455 mips_pci_io_size = TX4927_PCIIO_SIZE;
456 mips_pci_mem_base = TX4927_PCIMEM;
457 mips_pci_mem_size = TX4927_PCIMEM_SIZE;
459 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
460 "0x%08lx=mips_pci_io_base\n",
462 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
463 "0x%08lx=mips_pci_io_size\n",
465 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
466 "0x%08lx=mips_pci_mem_base\n",
468 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
469 "0x%08lx=mips_pci_mem_size\n",
471 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
472 "0x%08lx=pci_io_resource.start\n",
473 pci_io_resource.start);
474 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
475 "0x%08lx=pci_io_resource.end\n",
476 pci_io_resource.end);
477 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
478 "0x%08lx=pci_mem_resource.start\n",
479 pci_mem_resource.start);
480 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
481 "0x%08lx=pci_mem_resource.end\n",
482 pci_mem_resource.end);
483 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
484 "0x%08lx=mips_io_port_base",
488 ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
490 (unsigned short) (tx4927_pcicptr->pciid >> 16),
491 (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
492 (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
494 ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
498 printk("%s PCIC --%s PCICLK:", toshiba_name,
499 (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
500 if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
502 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
503 switch ((unsigned long) tx4927_ccfgptr->
504 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
505 case TX4937_CCFG_PCIDIVMODE_4:
506 pciclk = tx4927_cpu_clock / 4;
508 case TX4937_CCFG_PCIDIVMODE_4_5:
509 pciclk = tx4927_cpu_clock * 2 / 9;
511 case TX4937_CCFG_PCIDIVMODE_5:
512 pciclk = tx4927_cpu_clock / 5;
514 case TX4937_CCFG_PCIDIVMODE_5_5:
515 pciclk = tx4927_cpu_clock * 2 / 11;
517 case TX4937_CCFG_PCIDIVMODE_8:
518 pciclk = tx4927_cpu_clock / 8;
520 case TX4937_CCFG_PCIDIVMODE_9:
521 pciclk = tx4927_cpu_clock / 9;
523 case TX4937_CCFG_PCIDIVMODE_10:
524 pciclk = tx4927_cpu_clock / 10;
526 case TX4937_CCFG_PCIDIVMODE_11:
527 pciclk = tx4927_cpu_clock / 11;
532 switch ((unsigned long) tx4927_ccfgptr->
533 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
534 case TX4927_CCFG_PCIDIVMODE_2_5:
535 pciclk = tx4927_cpu_clock * 2 / 5;
537 case TX4927_CCFG_PCIDIVMODE_3:
538 pciclk = tx4927_cpu_clock / 3;
540 case TX4927_CCFG_PCIDIVMODE_5:
541 pciclk = tx4927_cpu_clock / 5;
543 case TX4927_CCFG_PCIDIVMODE_6:
544 pciclk = tx4927_cpu_clock / 6;
548 printk("Internal(%dMHz)", pciclk / 1000000);
551 int pciclk_setting = *tx4927_pci_clk_ptr;
552 switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
553 case TX4927_PCI_CLK_33:
556 case TX4927_PCI_CLK_25:
559 case TX4927_PCI_CLK_66:
562 case TX4927_PCI_CLK_50:
566 printk("External(%dMHz)", pciclk / 1000000);
572 /* GB->PCI mappings */
573 tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
574 tx4927_pcicptr->g2piogbase = mips_pci_io_base |
576 TX4927_PCIC_G2PIOGBASE_ECHG
578 TX4927_PCIC_G2PIOGBASE_BSDIS
582 tx4927_pcicptr->g2piopbase = 0;
584 tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
585 tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
587 TX4927_PCIC_G2PMnGBASE_ECHG
589 TX4927_PCIC_G2PMnGBASE_BSDIS
592 tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
594 tx4927_pcicptr->g2pmmask[1] = 0;
595 tx4927_pcicptr->g2pmgbase[1] = 0;
596 tx4927_pcicptr->g2pmpbase[1] = 0;
597 tx4927_pcicptr->g2pmmask[2] = 0;
598 tx4927_pcicptr->g2pmgbase[2] = 0;
599 tx4927_pcicptr->g2pmpbase[2] = 0;
602 /* PCI->GB mappings (I/O 256B) */
603 tx4927_pcicptr->p2giopbase = 0; /* 256B */
605 /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
606 tx4927_pcicptr->p2gm0plbase = 0;
607 tx4927_pcicptr->p2gm0pubase = 0;
608 tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
610 TX4927_PCIC_P2GMnGBASE_TECHG
612 TX4927_PCIC_P2GMnGBASE_TBSDIS
616 /* PCI->GB mappings (MEM 16MB) -not used */
617 tx4927_pcicptr->p2gm1plbase = 0xffffffff;
618 tx4927_pcicptr->p2gm1pubase = 0xffffffff;
619 tx4927_pcicptr->p2gmgbase[1] = 0;
621 /* PCI->GB mappings (MEM 1MB) -not used */
622 tx4927_pcicptr->p2gm2pbase = 0xffffffff;
623 tx4927_pcicptr->p2gmgbase[2] = 0;
626 /* Enable Initiator Memory 0 Space, I/O Space, Config */
627 tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
628 tx4927_pcicptr->pciccfg |=
629 TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
630 TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
633 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
634 tx4927_pcicptr->pcicfg1 = 0;
636 if (tx4927_pcic_trdyto >= 0) {
637 tx4927_pcicptr->g2ptocnt &= ~0xff;
638 tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
641 /* Clear All Local Bus Status */
642 tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
643 /* Enable All Local Bus Interrupts */
644 tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
645 /* Clear All Initiator Status */
646 tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
647 /* Enable All Initiator Interrupts */
648 tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
649 /* Clear All PCI Status Error */
650 tx4927_pcicptr->pcistatus =
651 (tx4927_pcicptr->pcistatus & 0x0000ffff) |
652 (TX4927_PCIC_PCISTATUS_ALL << 16);
653 /* Enable All PCI Status Error Interrupts */
654 tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
656 /* PCIC Int => IRC IRQ16 */
657 tx4927_pcicptr->pcicfg2 =
658 (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
660 if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
663 /* Reset Bus Arbiter */
664 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
665 /* Enable Bus Arbiter */
666 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
669 tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
671 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
673 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
674 ":pci setup complete:\n");
675 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
678 #endif /* CONFIG_PCI */
680 static void __noreturn wait_forever(void)
687 void toshiba_rbtx4927_restart(char *command)
689 printk(KERN_NOTICE "System Rebooting...\n");
691 /* enable the s/w reset register */
692 writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE);
694 /* wait for enable to be seen */
695 while ((readb(RBTX4927_SW_RESET_ENABLE) &
696 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
699 writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO);
701 /* do something passive while waiting for reset */
708 void toshiba_rbtx4927_halt(void)
710 printk(KERN_NOTICE "System Halted\n");
716 void toshiba_rbtx4927_power_off(void)
718 toshiba_rbtx4927_halt();
722 void __init toshiba_rbtx4927_setup(void)
727 printk("CPU is %s\n", toshiba_name);
729 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
732 /* f/w leaves this on at startup */
733 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
734 ":Clearing STO_ERL.\n");
735 clear_c0_status(ST0_ERL);
737 /* enable caches -- HCP5 does this, pmon does not */
738 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
739 ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
740 cp0_config = read_c0_config();
741 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
742 write_c0_config(cp0_config);
744 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
746 extern void dump_cp0(char *);
747 dump_cp0("toshiba_rbtx4927_early_fw_fixup");
751 set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
752 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
753 ":mips_io_port_base=0x%08lx\n",
756 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
758 ioport_resource.end = 0xffffffff;
759 iomem_resource.end = 0xffffffff;
761 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
763 _machine_restart = toshiba_rbtx4927_restart;
764 _machine_halt = toshiba_rbtx4927_halt;
765 pm_power_off = toshiba_rbtx4927_power_off;
771 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
774 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
775 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
776 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
777 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
778 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
779 * i.e. S9[3]: ON (83MHz), OFF (100MHz)
782 * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
783 * PCIDIVMODE[10] is 0.
784 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
785 * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
786 * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
787 * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
788 * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
789 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
792 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
793 "ccfg is %lx, PCIDIVMODE is %x\n",
794 (unsigned long) tx4927_ccfgptr->ccfg,
795 (unsigned long) tx4927_ccfgptr->ccfg &
796 (mips_machtype == MACH_TOSHIBA_RBTX4937 ?
797 TX4937_CCFG_PCIDIVMODE_MASK :
798 TX4927_CCFG_PCIDIVMODE_MASK));
800 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
801 "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
802 (unsigned long) tx4927_ccfgptr->
803 ccfg & TX4927_CCFG_PCI66,
804 (unsigned long) tx4927_ccfgptr->
805 ccfg & TX4927_CCFG_PCIMIDE,
806 (unsigned long) tx4927_ccfgptr->
807 ccfg & TX4927_CCFG_PCIXARB);
809 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
810 switch ((unsigned long)tx4927_ccfgptr->
811 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
812 case TX4937_CCFG_PCIDIVMODE_8:
813 case TX4937_CCFG_PCIDIVMODE_4:
814 tx4927_cpu_clock = 266666666; /* 266MHz */
816 case TX4937_CCFG_PCIDIVMODE_9:
817 case TX4937_CCFG_PCIDIVMODE_4_5:
818 tx4927_cpu_clock = 300000000; /* 300MHz */
821 tx4927_cpu_clock = 333333333; /* 333MHz */
824 switch ((unsigned long)tx4927_ccfgptr->
825 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
826 case TX4927_CCFG_PCIDIVMODE_2_5:
827 case TX4927_CCFG_PCIDIVMODE_5:
828 tx4927_cpu_clock = 166666666; /* 166MHz */
831 tx4927_cpu_clock = 200000000; /* 200MHz */
835 /* enable Timeout BusError */
836 if (tx4927_ccfg_toeon)
837 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
840 if (tx4927_using_backplane == 1)
841 printk("backplane board IS installed\n");
843 printk("No Backplane \n");
845 /* this is on ISA bus behind PCI bus, so need PCI up first */
846 #ifdef CONFIG_TOSHIBA_FPCIB0
848 if (tx4927_using_backplane) {
849 TOSHIBA_RBTX4927_SETUP_DPRINTK
850 (TOSHIBA_RBTX4927_SETUP_SETUP,
853 TOSHIBA_RBTX4927_SETUP_DPRINTK
854 (TOSHIBA_RBTX4927_SETUP_SETUP,
855 ":smsc_fdc37m81x_init()\n");
856 smsc_fdc37m81x_init(0x3f0);
858 TOSHIBA_RBTX4927_SETUP_DPRINTK
859 (TOSHIBA_RBTX4927_SETUP_SETUP,
860 ":smsc_fdc37m81x_config_beg()\n");
861 smsc_fdc37m81x_config_beg();
863 TOSHIBA_RBTX4927_SETUP_DPRINTK
864 (TOSHIBA_RBTX4927_SETUP_SETUP,
865 ":smsc_fdc37m81x_config_set(KBD)\n");
866 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
868 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
869 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
870 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
873 smsc_fdc37m81x_config_end();
874 TOSHIBA_RBTX4927_SETUP_DPRINTK
875 (TOSHIBA_RBTX4927_SETUP_SETUP,
876 ":smsc_fdc37m81x_config_end()\n");
878 TOSHIBA_RBTX4927_SETUP_DPRINTK
879 (TOSHIBA_RBTX4927_SETUP_SETUP,
880 ":fpcibo=not_found\n");
885 TOSHIBA_RBTX4927_SETUP_DPRINTK
886 (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
890 #endif /* CONFIG_PCI */
892 #ifdef CONFIG_SERIAL_TXX9
894 extern int early_serial_txx9_setup(struct uart_port *port);
896 struct uart_port req;
897 for(i = 0; i < 2; i++) {
898 memset(&req, 0, sizeof(req));
900 req.iotype = UPIO_MEM;
901 req.membase = (char *)(0xff1ff300 + i * 0x100);
902 req.mapbase = 0xff1ff300 + i * 0x100;
903 req.irq = TX4927_IRQ_PIC_BEG + 8 + i;
904 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
905 req.uartclk = 50000000;
906 early_serial_txx9_setup(&req);
909 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
910 argptr = prom_getcmdline();
911 if (strstr(argptr, "console=") == NULL) {
912 strcat(argptr, " console=ttyS0,38400");
917 #ifdef CONFIG_ROOT_NFS
918 argptr = prom_getcmdline();
919 if (strstr(argptr, "root=") == NULL) {
920 strcat(argptr, " root=/dev/nfs rw");
926 argptr = prom_getcmdline();
927 if (strstr(argptr, "ip=") == NULL) {
928 strcat(argptr, " ip=any");
933 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
938 toshiba_rbtx4927_time_init(void)
940 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n");
942 mips_hpt_frequency = tx4927_cpu_clock / 2;
944 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n");
948 static int __init toshiba_rbtx4927_rtc_init(void)
950 static struct resource __initdata res = {
952 .end = 0x1c010000 + 0x800 - 1,
953 .flags = IORESOURCE_MEM,
955 struct platform_device *dev =
956 platform_device_register_simple("rtc-ds1742", -1, &res, 1);
957 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
959 device_initcall(toshiba_rbtx4927_rtc_init);
961 static int __init rbtx4927_ne_init(void)
963 static struct resource __initdata res[] = {
965 .start = RBTX4927_RTL_8019_BASE,
966 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
967 .flags = IORESOURCE_IO,
969 .start = RBTX4927_RTL_8019_IRQ,
970 .flags = IORESOURCE_IRQ,
973 struct platform_device *dev =
974 platform_device_register_simple("ne", -1,
975 res, ARRAY_SIZE(res));
976 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
978 device_initcall(rbtx4927_ne_init);