arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c

   1 /*
   2  * Toshiba rbtx4927 specific setup
   3  *
   4  * Author: MontaVista Software, Inc.
   5  *         source@mvista.com
   6  *
   7  * Copyright 2001-2002 MontaVista Software Inc.
   8  *
   9  * Copyright (C) 1996, 97, 2001, 04  Ralf Baechle (ralf@linux-mips.org)
  10  * Copyright (C) 2000 RidgeRun, Inc.
  11  * Author: RidgeRun, Inc.
  12  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
  13  *
  14  * Copyright 2001 MontaVista Software Inc.
  15  * Author: jsun@mvista.com or jsun@junsun.net
  16  *
  17  * Copyright 2002 MontaVista Software Inc.
  18  * Author: Michael Pruznick, michael_pruznick@mvista.com
  19  *
  20  * Copyright (C) 2000-2001 Toshiba Corporation
  21  *
  22  * Copyright (C) 2004 MontaVista Software Inc.
  23  * Author: Manish Lachwani, mlachwani@mvista.com
  24  *
  25  *  This program is free software; you can redistribute it and/or modify it
  26  *  under the terms of the GNU General Public License as published by the
  27  *  Free Software Foundation; either version 2 of the License, or (at your
  28  *  option) any later version.
  29  *
  30  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  31  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  32  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  33  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  34  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  35  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  36  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  38  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  39  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  *  You should have received a copy of the GNU General Public License along
  42  *  with this program; if not, write to the Free Software Foundation, Inc.,
  43  *  675 Mass Ave, Cambridge, MA 02139, USA.
  44  */
  45 #include <linux/init.h>
  46 #include <linux/kernel.h>
  47 #include <linux/types.h>
  48 #include <linux/ioport.h>
  49 #include <linux/interrupt.h>
  50 #include <linux/pci.h>
  51 #include <linux/pm.h>
  52 #include <linux/platform_device.h>
  53
  54 #include <asm/bootinfo.h>
  55 #include <asm/io.h>
  56 #include <asm/processor.h>
  57 #include <asm/reboot.h>
  58 #include <asm/time.h>
  59 #include <asm/txx9tmr.h>
  60 #ifdef CONFIG_TOSHIBA_FPCIB0
  61 #include <asm/tx4927/smsc_fdc37m81x.h>
  62 #endif
  63 #include <asm/tx4927/toshiba_rbtx4927.h>
  64 #ifdef CONFIG_PCI
  65 #include <asm/tx4927/tx4927_pci.h>
  66 #endif
  67 #ifdef CONFIG_SERIAL_TXX9
  68 #include <linux/serial_core.h>
  69 #endif
  70
  71 #undef TOSHIBA_RBTX4927_SETUP_DEBUG
  72
  73 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
  74 #define TOSHIBA_RBTX4927_SETUP_SETUP       ( 1 <<  4 )
  75 #define TOSHIBA_RBTX4927_SETUP_PCIBIOS     ( 1 <<  7 )
  76 #define TOSHIBA_RBTX4927_SETUP_PCI1        ( 1 <<  8 )
  77 #define TOSHIBA_RBTX4927_SETUP_PCI2        ( 1 <<  9 )
  78
  79 #define TOSHIBA_RBTX4927_SETUP_ALL         0xffffffff
  80 #endif
  81
  82 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
  83 static const u32 toshiba_rbtx4927_setup_debug_flag =
  84     (TOSHIBA_RBTX4927_SETUP_SETUP |
  85      | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
  86      TOSHIBA_RBTX4927_SETUP_PCI2);
  87 #endif
  88
  89 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
  90 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \
  91         if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \
  92         { \
  93            char tmp[100]; \
  94            sprintf( tmp, str ); \
  95            printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
  96         }
  97 #else
  98 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag, str...)
  99 #endif
 100
 101 /* These functions are used for rebooting or halting the machine*/
 102 extern void toshiba_rbtx4927_restart(char *command);
 103 extern void toshiba_rbtx4927_halt(void);
 104 extern void toshiba_rbtx4927_power_off(void);
 105
 106 int tx4927_using_backplane = 0;
 107
 108 extern void toshiba_rbtx4927_irq_setup(void);
 109
 110 char *prom_getcmdline(void);
 111
 112 #ifdef CONFIG_PCI
 113 #undef TX4927_SUPPORT_COMMAND_IO
 114 #undef  TX4927_SUPPORT_PCI_66
 115 int tx4927_cpu_clock = 100000000;       /* 100MHz */
 116 unsigned long mips_pci_io_base;
 117 unsigned long mips_pci_io_size;
 118 unsigned long mips_pci_mem_base;
 119 unsigned long mips_pci_mem_size;
 120 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
 121 unsigned long mips_pci_io_pciaddr = 0;
 122 unsigned long mips_memory_upper;
 123 static int tx4927_ccfg_toeon = 1;
 124 static int tx4927_pcic_trdyto = 0;      /* default: disabled */
 125 unsigned long tx4927_ce_base[8];
 126 void tx4927_reset_pci_pcic(void);
 127 int tx4927_pci66 = 0;           /* 0:auto */
 128 #endif
 129
 130 char *toshiba_name = "";
 131
 132 #ifdef CONFIG_PCI
 133 extern struct pci_controller tx4927_controller;
 134
 135 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
 136                                     int top_bus, int busnr, int devfn)
 137 {
 138         static struct pci_dev dev;
 139         static struct pci_bus bus;
 140
 141         dev.sysdata = (void *)hose;
 142         dev.devfn = devfn;
 143         bus.number = busnr;
 144         bus.ops = hose->pci_ops;
 145         bus.parent = NULL;
 146         dev.bus = &bus;
 147
 148         return &dev;
 149 }
 150
 151 #define EARLY_PCI_OP(rw, size, type)                                    \
 152 static int early_##rw##_config_##size(struct pci_controller *hose,      \
 153         int top_bus, int bus, int devfn, int offset, type value)        \
 154 {                                                                       \
 155         return pci_##rw##_config_##size(                                \
 156                 fake_pci_dev(hose, top_bus, bus, devfn),                \
 157                 offset, value);                                         \
 158 }
 159
 160 EARLY_PCI_OP(read, byte, u8 *)
 161 EARLY_PCI_OP(read, dword, u32 *)
 162 EARLY_PCI_OP(write, byte, u8)
 163 EARLY_PCI_OP(write, dword, u32)
 164
 165 static int __init tx4927_pcibios_init(void)
 166 {
 167         unsigned int id;
 168         u32 pci_devfn;
 169         int devfn_start = 0;
 170         int devfn_stop = 0xff;
 171         int busno = 0; /* One bus on the Toshiba */
 172         struct pci_controller *hose = &tx4927_controller;
 173
 174         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 175                                        "-\n");
 176
 177         for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
 178                 early_read_config_dword(hose, busno, busno, pci_devfn,
 179                                         PCI_VENDOR_ID, &id);
 180
 181                 if (id == 0xffffffff) {
 182                         continue;
 183                 }
 184
 185                 if (id == 0x94601055) {
 186                         u8 v08_64;
 187                         u32 v32_b0;
 188                         u8 v08_e1;
 189 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 190                         char *s = " sb/isa --";
 191 #endif
 192
 193                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 194                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
 195                              s);
 196
 197                         early_read_config_byte(hose, busno, busno,
 198                                                pci_devfn, 0x64, &v08_64);
 199                         early_read_config_dword(hose, busno, busno,
 200                                                 pci_devfn, 0xb0, &v32_b0);
 201                         early_read_config_byte(hose, busno, busno,
 202                                                pci_devfn, 0xe1, &v08_e1);
 203
 204                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 205                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 206                              ":%s beg 0x64 = 0x%02x\n", s, v08_64);
 207                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 208                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 209                              ":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
 210                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 211                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 212                              ":%s beg 0xe1 = 0x%02x\n", s, v08_e1);
 213
 214                         /* serial irq control */
 215                         v08_64 = 0xd0;
 216
 217                         /* serial irq pin */
 218                         v32_b0 |= 0x00010000;
 219
 220                         /* ide irq on isa14 */
 221                         v08_e1 &= 0xf0;
 222                         v08_e1 |= 0x0d;
 223
 224                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 225                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 226                              ":%s mid 0x64 = 0x%02x\n", s, v08_64);
 227                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 228                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 229                              ":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
 230                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 231                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 232                              ":%s mid 0xe1 = 0x%02x\n", s, v08_e1);
 233
 234                         early_write_config_byte(hose, busno, busno,
 235                                                 pci_devfn, 0x64, v08_64);
 236                         early_write_config_dword(hose, busno, busno,
 237                                                  pci_devfn, 0xb0, v32_b0);
 238                         early_write_config_byte(hose, busno, busno,
 239                                                 pci_devfn, 0xe1, v08_e1);
 240
 241 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 242                         {
 243                                 early_read_config_byte(hose, busno, busno,
 244                                                        pci_devfn, 0x64,
 245                                                        &v08_64);
 246                                 early_read_config_dword(hose, busno, busno,
 247                                                         pci_devfn, 0xb0,
 248                                                         &v32_b0);
 249                                 early_read_config_byte(hose, busno, busno,
 250                                                        pci_devfn, 0xe1,
 251                                                        &v08_e1);
 252
 253                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 254                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 255                                      ":%s end 0x64 = 0x%02x\n", s, v08_64);
 256                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 257                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 258                                      ":%s end 0xb0 = 0x%02x\n", s, v32_b0);
 259                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 260                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 261                                      ":%s end 0xe1 = 0x%02x\n", s, v08_e1);
 262                         }
 263 #endif
 264
 265                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 266                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
 267                              s);
 268                 }
 269
 270                 if (id == 0x91301055) {
 271                         u8 v08_04;
 272                         u8 v08_09;
 273                         u8 v08_41;
 274                         u8 v08_43;
 275                         u8 v08_5c;
 276 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 277                         char *s = " sb/ide --";
 278 #endif
 279
 280                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 281                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
 282                              s);
 283
 284                         early_read_config_byte(hose, busno, busno,
 285                                                pci_devfn, 0x04, &v08_04);
 286                         early_read_config_byte(hose, busno, busno,
 287                                                pci_devfn, 0x09, &v08_09);
 288                         early_read_config_byte(hose, busno, busno,
 289                                                pci_devfn, 0x41, &v08_41);
 290                         early_read_config_byte(hose, busno, busno,
 291                                                pci_devfn, 0x43, &v08_43);
 292                         early_read_config_byte(hose, busno, busno,
 293                                                pci_devfn, 0x5c, &v08_5c);
 294
 295                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 296                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 297                              ":%s beg 0x04 = 0x%02x\n", s, v08_04);
 298                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 299                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 300                              ":%s beg 0x09 = 0x%02x\n", s, v08_09);
 301                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 302                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 303                              ":%s beg 0x41 = 0x%02x\n", s, v08_41);
 304                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 305                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 306                              ":%s beg 0x43 = 0x%02x\n", s, v08_43);
 307                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 308                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 309                              ":%s beg 0x5c = 0x%02x\n", s, v08_5c);
 310
 311                         /* enable ide master/io */
 312                         v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
 313
 314                         /* enable ide native mode */
 315                         v08_09 |= 0x05;
 316
 317                         /* enable primary ide */
 318                         v08_41 |= 0x80;
 319
 320                         /* enable secondary ide */
 321                         v08_43 |= 0x80;
 322
 323                         /*
 324                          * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
 325                          *
 326                          * This line of code is intended to provide the user with a work
 327                          * around solution to the anomalies cited in SMSC's anomaly sheet
 328                          * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
 329                          *
 330                          * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
 331                          */
 332                         v08_5c |= 0x01;
 333
 334                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 335                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 336                              ":%s mid 0x04 = 0x%02x\n", s, v08_04);
 337                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 338                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 339                              ":%s mid 0x09 = 0x%02x\n", s, v08_09);
 340                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 341                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 342                              ":%s mid 0x41 = 0x%02x\n", s, v08_41);
 343                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 344                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 345                              ":%s mid 0x43 = 0x%02x\n", s, v08_43);
 346                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 347                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 348                              ":%s mid 0x5c = 0x%02x\n", s, v08_5c);
 349
 350                         early_write_config_byte(hose, busno, busno,
 351                                                 pci_devfn, 0x5c, v08_5c);
 352                         early_write_config_byte(hose, busno, busno,
 353                                                 pci_devfn, 0x04, v08_04);
 354                         early_write_config_byte(hose, busno, busno,
 355                                                 pci_devfn, 0x09, v08_09);
 356                         early_write_config_byte(hose, busno, busno,
 357                                                 pci_devfn, 0x41, v08_41);
 358                         early_write_config_byte(hose, busno, busno,
 359                                                 pci_devfn, 0x43, v08_43);
 360
 361 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 362                         {
 363                                 early_read_config_byte(hose, busno, busno,
 364                                                        pci_devfn, 0x04,
 365                                                        &v08_04);
 366                                 early_read_config_byte(hose, busno, busno,
 367                                                        pci_devfn, 0x09,
 368                                                        &v08_09);
 369                                 early_read_config_byte(hose, busno, busno,
 370                                                        pci_devfn, 0x41,
 371                                                        &v08_41);
 372                                 early_read_config_byte(hose, busno, busno,
 373                                                        pci_devfn, 0x43,
 374                                                        &v08_43);
 375                                 early_read_config_byte(hose, busno, busno,
 376                                                        pci_devfn, 0x5c,
 377                                                        &v08_5c);
 378
 379                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 380                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 381                                      ":%s end 0x04 = 0x%02x\n", s, v08_04);
 382                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 383                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 384                                      ":%s end 0x09 = 0x%02x\n", s, v08_09);
 385                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 386                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 387                                      ":%s end 0x41 = 0x%02x\n", s, v08_41);
 388                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 389                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 390                                      ":%s end 0x43 = 0x%02x\n", s, v08_43);
 391                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 392                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 393                                      ":%s end 0x5c = 0x%02x\n", s, v08_5c);
 394                         }
 395 #endif
 396
 397                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 398                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
 399                              s);
 400                 }
 401
 402         }
 403
 404         register_pci_controller(&tx4927_controller);
 405         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 406                                        "+\n");
 407
 408         return 0;
 409 }
 410
 411 arch_initcall(tx4927_pcibios_init);
 412
 413 extern struct resource pci_io_resource;
 414 extern struct resource pci_mem_resource;
 415
 416 void __init tx4927_pci_setup(void)
 417 {
 418         static int called = 0;
 419         extern unsigned int tx4927_get_mem_size(void);
 420
 421         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");
 422
 423         mips_memory_upper = tx4927_get_mem_size() << 20;
 424         mips_memory_upper += KSEG0;
 425         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 426                                        "0x%08lx=mips_memory_upper\n",
 427                                        mips_memory_upper);
 428         mips_pci_io_base = TX4927_PCIIO;
 429         mips_pci_io_size = TX4927_PCIIO_SIZE;
 430         mips_pci_mem_base = TX4927_PCIMEM;
 431         mips_pci_mem_size = TX4927_PCIMEM_SIZE;
 432
 433         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 434                                        "0x%08lx=mips_pci_io_base\n",
 435                                        mips_pci_io_base);
 436         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 437                                        "0x%08lx=mips_pci_io_size\n",
 438                                        mips_pci_io_size);
 439         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 440                                        "0x%08lx=mips_pci_mem_base\n",
 441                                        mips_pci_mem_base);
 442         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 443                                        "0x%08lx=mips_pci_mem_size\n",
 444                                        mips_pci_mem_size);
 445         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 446                                        "0x%08lx=pci_io_resource.start\n",
 447                                        pci_io_resource.start);
 448         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 449                                        "0x%08lx=pci_io_resource.end\n",
 450                                        pci_io_resource.end);
 451         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 452                                        "0x%08lx=pci_mem_resource.start\n",
 453                                        pci_mem_resource.start);
 454         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 455                                        "0x%08lx=pci_mem_resource.end\n",
 456                                        pci_mem_resource.end);
 457         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 458                                        "0x%08lx=mips_io_port_base",
 459                                        mips_io_port_base);
 460         if (!called) {
 461                 printk
 462                     ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
 463                      toshiba_name,
 464                      (unsigned short) (tx4927_pcicptr->pciid >> 16),
 465                      (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
 466                      (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
 467                      (!(tx4927_ccfgptr->
 468                         ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
 469                      "Internal");
 470                 called = 1;
 471         }
 472         printk("%s PCIC --%s PCICLK:", toshiba_name,
 473                (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
 474         if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
 475                 int pciclk = 0;
 476                 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
 477                         switch ((unsigned long) tx4927_ccfgptr->
 478                                 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
 479                         case TX4937_CCFG_PCIDIVMODE_4:
 480                                 pciclk = tx4927_cpu_clock / 4;
 481                                 break;
 482                         case TX4937_CCFG_PCIDIVMODE_4_5:
 483                                 pciclk = tx4927_cpu_clock * 2 / 9;
 484                                 break;
 485                         case TX4937_CCFG_PCIDIVMODE_5:
 486                                 pciclk = tx4927_cpu_clock / 5;
 487                                 break;
 488                         case TX4937_CCFG_PCIDIVMODE_5_5:
 489                                 pciclk = tx4927_cpu_clock * 2 / 11;
 490                                 break;
 491                         case TX4937_CCFG_PCIDIVMODE_8:
 492                                 pciclk = tx4927_cpu_clock / 8;
 493                                 break;
 494                         case TX4937_CCFG_PCIDIVMODE_9:
 495                                 pciclk = tx4927_cpu_clock / 9;
 496                                 break;
 497                         case TX4937_CCFG_PCIDIVMODE_10:
 498                                 pciclk = tx4927_cpu_clock / 10;
 499                                 break;
 500                         case TX4937_CCFG_PCIDIVMODE_11:
 501                                 pciclk = tx4927_cpu_clock / 11;
 502                                 break;
 503                         }
 504
 505                 else
 506                         switch ((unsigned long) tx4927_ccfgptr->
 507                                 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
 508                         case TX4927_CCFG_PCIDIVMODE_2_5:
 509                                 pciclk = tx4927_cpu_clock * 2 / 5;
 510                                 break;
 511                         case TX4927_CCFG_PCIDIVMODE_3:
 512                                 pciclk = tx4927_cpu_clock / 3;
 513                                 break;
 514                         case TX4927_CCFG_PCIDIVMODE_5:
 515                                 pciclk = tx4927_cpu_clock / 5;
 516                                 break;
 517                         case TX4927_CCFG_PCIDIVMODE_6:
 518                                 pciclk = tx4927_cpu_clock / 6;
 519                                 break;
 520                         }
 521
 522                 printk("Internal(%dMHz)", pciclk / 1000000);
 523         } else {
 524                 int pciclk = 0;
 525                 int pciclk_setting = *tx4927_pci_clk_ptr;
 526                 switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
 527                 case TX4927_PCI_CLK_33:
 528                         pciclk = 33333333;
 529                         break;
 530                 case TX4927_PCI_CLK_25:
 531                         pciclk = 25000000;
 532                         break;
 533                 case TX4927_PCI_CLK_66:
 534                         pciclk = 66666666;
 535                         break;
 536                 case TX4927_PCI_CLK_50:
 537                         pciclk = 50000000;
 538                         break;
 539                 }
 540                 printk("External(%dMHz)", pciclk / 1000000);
 541         }
 542         printk("\n");
 543
 544
 545
 546         /* GB->PCI mappings */
 547         tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
 548         tx4927_pcicptr->g2piogbase = mips_pci_io_base |
 549 #ifdef __BIG_ENDIAN
 550             TX4927_PCIC_G2PIOGBASE_ECHG
 551 #else
 552             TX4927_PCIC_G2PIOGBASE_BSDIS
 553 #endif
 554             ;
 555
 556         tx4927_pcicptr->g2piopbase = 0;
 557
 558         tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
 559         tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
 560 #ifdef __BIG_ENDIAN
 561             TX4927_PCIC_G2PMnGBASE_ECHG
 562 #else
 563             TX4927_PCIC_G2PMnGBASE_BSDIS
 564 #endif
 565             ;
 566         tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
 567
 568         tx4927_pcicptr->g2pmmask[1] = 0;
 569         tx4927_pcicptr->g2pmgbase[1] = 0;
 570         tx4927_pcicptr->g2pmpbase[1] = 0;
 571         tx4927_pcicptr->g2pmmask[2] = 0;
 572         tx4927_pcicptr->g2pmgbase[2] = 0;
 573         tx4927_pcicptr->g2pmpbase[2] = 0;
 574
 575
 576         /* PCI->GB mappings (I/O 256B) */
 577         tx4927_pcicptr->p2giopbase = 0; /* 256B */
 578
 579         /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
 580         tx4927_pcicptr->p2gm0plbase = 0;
 581         tx4927_pcicptr->p2gm0pubase = 0;
 582         tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
 583 #ifdef __BIG_ENDIAN
 584             TX4927_PCIC_P2GMnGBASE_TECHG
 585 #else
 586             TX4927_PCIC_P2GMnGBASE_TBSDIS
 587 #endif
 588             ;
 589
 590         /* PCI->GB mappings (MEM 16MB) -not used */
 591         tx4927_pcicptr->p2gm1plbase = 0xffffffff;
 592         tx4927_pcicptr->p2gm1pubase = 0xffffffff;
 593         tx4927_pcicptr->p2gmgbase[1] = 0;
 594
 595         /* PCI->GB mappings (MEM 1MB) -not used */
 596         tx4927_pcicptr->p2gm2pbase = 0xffffffff;
 597         tx4927_pcicptr->p2gmgbase[2] = 0;
 598
 599
 600         /* Enable Initiator Memory 0 Space, I/O Space, Config */
 601         tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
 602         tx4927_pcicptr->pciccfg |=
 603             TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
 604             TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
 605
 606
 607         /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
 608         tx4927_pcicptr->pcicfg1 = 0;
 609
 610         if (tx4927_pcic_trdyto >= 0) {
 611                 tx4927_pcicptr->g2ptocnt &= ~0xff;
 612                 tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
 613         }
 614
 615         /* Clear All Local Bus Status */
 616         tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
 617         /* Enable All Local Bus Interrupts */
 618         tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
 619         /* Clear All Initiator Status */
 620         tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
 621         /* Enable All Initiator Interrupts */
 622         tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
 623         /* Clear All PCI Status Error */
 624         tx4927_pcicptr->pcistatus =
 625             (tx4927_pcicptr->pcistatus & 0x0000ffff) |
 626             (TX4927_PCIC_PCISTATUS_ALL << 16);
 627         /* Enable All PCI Status Error Interrupts */
 628         tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
 629
 630         /* PCIC Int => IRC IRQ16 */
 631         tx4927_pcicptr->pcicfg2 =
 632             (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
 633
 634         if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
 635                 /* XXX */
 636         } else {
 637                 /* Reset Bus Arbiter */
 638                 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
 639                 /* Enable Bus Arbiter */
 640                 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
 641         }
 642
 643         tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
 644             PCI_COMMAND_MEMORY |
 645             PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 646
 647         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 648                                        ":pci setup complete:\n");
 649         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
 650 }
 651
 652 #endif /* CONFIG_PCI */
 653
 654 static void __noreturn wait_forever(void)
 655 {
 656         while (1)
 657                 if (cpu_wait)
 658                         (*cpu_wait)();
 659 }
 660
 661 void toshiba_rbtx4927_restart(char *command)
 662 {
 663         printk(KERN_NOTICE "System Rebooting...\n");
 664
 665         /* enable the s/w reset register */
 666         writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE);
 667
 668         /* wait for enable to be seen */
 669         while ((readb(RBTX4927_SW_RESET_ENABLE) &
 670                 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
 671
 672         /* do a s/w reset */
 673         writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO);
 674
 675         /* do something passive while waiting for reset */
 676         local_irq_disable();
 677         wait_forever();
 678         /* no return */
 679 }
 680
 681
 682 void toshiba_rbtx4927_halt(void)
 683 {
 684         printk(KERN_NOTICE "System Halted\n");
 685         local_irq_disable();
 686         wait_forever();
 687         /* no return */
 688 }
 689
 690 void toshiba_rbtx4927_power_off(void)
 691 {
 692         toshiba_rbtx4927_halt();
 693         /* no return */
 694 }
 695
 696 void __init plat_mem_setup(void)
 697 {
 698         int i;
 699         u32 cp0_config;
 700         char *argptr;
 701
 702         printk("CPU is %s\n", toshiba_name);
 703
 704         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 705                                        "-\n");
 706
 707         /* f/w leaves this on at startup */
 708         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 709                                        ":Clearing STO_ERL.\n");
 710         clear_c0_status(ST0_ERL);
 711
 712         /* enable caches -- HCP5 does this, pmon does not */
 713         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 714                                        ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
 715         cp0_config = read_c0_config();
 716         cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
 717         write_c0_config(cp0_config);
 718
 719         set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
 720         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 721                                        ":mips_io_port_base=0x%08lx\n",
 722                                        mips_io_port_base);
 723
 724         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 725                                        ":Resource\n");
 726         ioport_resource.end = 0xffffffff;
 727         iomem_resource.end = 0xffffffff;
 728
 729         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 730                                        ":ResetRoutines\n");
 731         _machine_restart = toshiba_rbtx4927_restart;
 732         _machine_halt = toshiba_rbtx4927_halt;
 733         pm_power_off = toshiba_rbtx4927_power_off;
 734
 735         for (i = 0; i < TX4927_NR_TMR; i++)
 736                 txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
 737
 738 #ifdef CONFIG_PCI
 739
 740         /* PCIC */
 741         /*
 742            * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
 743            *
 744            * For TX4927:
 745            * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
 746            * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
 747            * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
 748            * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
 749            * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
 750            * i.e. S9[3]: ON (83MHz), OFF (100MHz)
 751            *
 752            * For TX4937:
 753            * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
 754            * PCIDIVMODE[10] is 0.
 755            * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
 756            * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
 757            * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
 758            * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
 759            * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
 760            * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
 761            *
 762          */
 763         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
 764                                        "ccfg is %lx, PCIDIVMODE is %x\n",
 765                                        (unsigned long) tx4927_ccfgptr->ccfg,
 766                                        (unsigned long) tx4927_ccfgptr->ccfg &
 767                                        (mips_machtype == MACH_TOSHIBA_RBTX4937 ?
 768                                         TX4937_CCFG_PCIDIVMODE_MASK :
 769                                         TX4927_CCFG_PCIDIVMODE_MASK));
 770
 771         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
 772                                        "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
 773                                        (unsigned long) tx4927_ccfgptr->
 774                                        ccfg & TX4927_CCFG_PCI66,
 775                                        (unsigned long) tx4927_ccfgptr->
 776                                        ccfg & TX4927_CCFG_PCIMIDE,
 777                                        (unsigned long) tx4927_ccfgptr->
 778                                        ccfg & TX4927_CCFG_PCIXARB);
 779
 780         if (mips_machtype == MACH_TOSHIBA_RBTX4937)
 781                 switch ((unsigned long)tx4927_ccfgptr->
 782                         ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
 783                 case TX4937_CCFG_PCIDIVMODE_8:
 784                 case TX4937_CCFG_PCIDIVMODE_4:
 785                         tx4927_cpu_clock = 266666666;   /* 266MHz */
 786                         break;
 787                 case TX4937_CCFG_PCIDIVMODE_9:
 788                 case TX4937_CCFG_PCIDIVMODE_4_5:
 789                         tx4927_cpu_clock = 300000000;   /* 300MHz */
 790                         break;
 791                 default:
 792                         tx4927_cpu_clock = 333333333;   /* 333MHz */
 793                 }
 794         else
 795                 switch ((unsigned long)tx4927_ccfgptr->
 796                         ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
 797                 case TX4927_CCFG_PCIDIVMODE_2_5:
 798                 case TX4927_CCFG_PCIDIVMODE_5:
 799                         tx4927_cpu_clock = 166666666;   /* 166MHz */
 800                         break;
 801                 default:
 802                         tx4927_cpu_clock = 200000000;   /* 200MHz */
 803                 }
 804
 805         /* CCFG */
 806         /* enable Timeout BusError */
 807         if (tx4927_ccfg_toeon)
 808                 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
 809
 810         tx4927_pci_setup();
 811         if (tx4927_using_backplane == 1)
 812                 printk("backplane board IS installed\n");
 813         else
 814                 printk("No Backplane \n");
 815
 816         /* this is on ISA bus behind PCI bus, so need PCI up first */
 817 #ifdef CONFIG_TOSHIBA_FPCIB0
 818         {
 819                 if (tx4927_using_backplane) {
 820                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 821                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 822                              ":fpcibo=yes\n");
 823
 824                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 825                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 826                              ":smsc_fdc37m81x_init()\n");
 827                         smsc_fdc37m81x_init(0x3f0);
 828
 829                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 830                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 831                              ":smsc_fdc37m81x_config_beg()\n");
 832                         smsc_fdc37m81x_config_beg();
 833
 834                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 835                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 836                              ":smsc_fdc37m81x_config_set(KBD)\n");
 837                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
 838                                                   SMSC_FDC37M81X_KBD);
 839                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
 840                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
 841                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
 842                                                   1);
 843
 844                         smsc_fdc37m81x_config_end();
 845                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 846                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 847                              ":smsc_fdc37m81x_config_end()\n");
 848                 } else {
 849                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 850                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 851                              ":fpcibo=not_found\n");
 852                 }
 853         }
 854 #else
 855         {
 856                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 857                     (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
 858         }
 859 #endif
 860
 861 #endif /* CONFIG_PCI */
 862
 863 #ifdef CONFIG_SERIAL_TXX9
 864         {
 865                 extern int early_serial_txx9_setup(struct uart_port *port);
 866                 struct uart_port req;
 867                 for(i = 0; i < 2; i++) {
 868                         memset(&req, 0, sizeof(req));
 869                         req.line = i;
 870                         req.iotype = UPIO_MEM;
 871                         req.membase = (char *)(0xff1ff300 + i * 0x100);
 872                         req.mapbase = 0xff1ff300 + i * 0x100;
 873                         req.irq = TX4927_IRQ_PIC_BEG + 8 + i;
 874                         req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
 875                         req.uartclk = 50000000;
 876                         early_serial_txx9_setup(&req);
 877                 }
 878         }
 879 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
 880         argptr = prom_getcmdline();
 881         if (strstr(argptr, "console=") == NULL) {
 882                 strcat(argptr, " console=ttyS0,38400");
 883         }
 884 #endif
 885 #endif
 886
 887 #ifdef CONFIG_ROOT_NFS
 888         argptr = prom_getcmdline();
 889         if (strstr(argptr, "root=") == NULL) {
 890                 strcat(argptr, " root=/dev/nfs rw");
 891         }
 892 #endif
 893
 894
 895 #ifdef CONFIG_IP_PNP
 896         argptr = prom_getcmdline();
 897         if (strstr(argptr, "ip=") == NULL) {
 898                 strcat(argptr, " ip=any");
 899         }
 900 #endif
 901
 902
 903         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 904                                "+\n");
 905 }
 906
 907 void __init plat_time_init(void)
 908 {
 909         mips_hpt_frequency = tx4927_cpu_clock / 2;
 910         if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS)
 911                 txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
 912                                      TXX9_IRQ_BASE + 17,
 913                                      50000000);
 914 }
 915
 916 static int __init toshiba_rbtx4927_rtc_init(void)
 917 {
 918         static struct resource __initdata res = {
 919                 .start  = 0x1c010000,
 920                 .end    = 0x1c010000 + 0x800 - 1,
 921                 .flags  = IORESOURCE_MEM,
 922         };
 923         struct platform_device *dev =
 924                 platform_device_register_simple("rtc-ds1742", -1, &res, 1);
 925         return IS_ERR(dev) ? PTR_ERR(dev) : 0;
 926 }
 927 device_initcall(toshiba_rbtx4927_rtc_init);
 928
 929 static int __init rbtx4927_ne_init(void)
 930 {
 931         static struct resource __initdata res[] = {
 932                 {
 933                         .start  = RBTX4927_RTL_8019_BASE,
 934                         .end    = RBTX4927_RTL_8019_BASE + 0x20 - 1,
 935                         .flags  = IORESOURCE_IO,
 936                 }, {
 937                         .start  = RBTX4927_RTL_8019_IRQ,
 938                         .flags  = IORESOURCE_IRQ,
 939                 }
 940         };
 941         struct platform_device *dev =
 942                 platform_device_register_simple("ne", -1,
 943                                                 res, ARRAY_SIZE(res));
 944         return IS_ERR(dev) ? PTR_ERR(dev) : 0;
 945 }
 946 device_initcall(rbtx4927_ne_init);