2 * linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
4 * Toshiba RBTX4927 specific interrupt handlers
6 * Author: MontaVista Software, Inc.
9 * Copyright 2001-2002 MontaVista Software Inc.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
24 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 01 RBTX4927-ISA/01 PS2/Keyboard
35 02 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15)
45 12 RBTX4927-ISA/12 PS2/Mouse (not supported at this time)
47 14 RBTX4927-ISA/14 IDE
50 16 TX4927-CP0/00 Software 0
51 17 TX4927-CP0/01 Software 1
52 18 TX4927-CP0/02 Cascade TX4927-CP0
53 19 TX4927-CP0/03 Multiplexed -- do not use
54 20 TX4927-CP0/04 Multiplexed -- do not use
55 21 TX4927-CP0/05 Multiplexed -- do not use
56 22 TX4927-CP0/06 Multiplexed -- do not use
57 23 TX4927-CP0/07 CPU TIMER
62 27 TX4927-PIC/03 Cascade RBTX4927-IOC
64 29 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet
67 32 TX4927-PIC/08 TX4927 SerialIO Channel 0
68 33 TX4927-PIC/09 TX4927 SerialIO Channel 1
75 40 TX4927-PIC/16 TX4927 PCI PCI-C
81 46 TX4927-PIC/22 TX4927 PCI PCI-ERR
82 47 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used)
92 56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed) [RTL-8139=PJ4]
93 57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed) [RTL-8139=PJ5]
94 58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported]
95 59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4) [RTL-8139=PJ6]
102 SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
103 SouthBridge/ISA/pin=0 no pci irq used by this device
104 SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14
105 SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59
106 SouthBridge/PMC/pin=0 no pci irq used by this device
107 SuperIO/PS2/Keyboard, using INTR via ISA IRQ1
108 SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported)
109 JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6
112 #include <linux/init.h>
113 #include <linux/types.h>
114 #include <linux/interrupt.h>
116 #ifdef CONFIG_TOSHIBA_FPCIB0
117 #include <asm/i8259.h>
119 #include <asm/tx4927/toshiba_rbtx4927.h>
121 #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0
122 #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7
124 #define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */
125 #define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */
127 #define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC
128 #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2)
130 extern int tx4927_using_backplane;
132 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
133 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
135 #define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
136 static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
137 .name = TOSHIBA_RBTX4927_IOC_NAME,
138 .ack = toshiba_rbtx4927_irq_ioc_disable,
139 .mask = toshiba_rbtx4927_irq_ioc_disable,
140 .mask_ack = toshiba_rbtx4927_irq_ioc_disable,
141 .unmask = toshiba_rbtx4927_irq_ioc_enable,
143 #define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL
144 #define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL
146 int toshiba_rbtx4927_irq_nested(int sw_irq)
150 level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
152 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1;
153 #ifdef CONFIG_TOSHIBA_FPCIB0
154 if (sw_irq == TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC &&
155 tx4927_using_backplane) {
156 int irq = i8259_irq();
165 static struct irqaction toshiba_rbtx4927_irq_ioc_action = {
166 .handler = no_action,
167 .flags = IRQF_SHARED,
168 .mask = CPU_MASK_NONE,
169 .name = TOSHIBA_RBTX4927_IOC_NAME
172 static void __init toshiba_rbtx4927_irq_ioc_init(void)
176 for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG;
177 i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++)
178 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
181 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
182 &toshiba_rbtx4927_irq_ioc_action);
185 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
189 v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
190 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
191 writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB);
194 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
198 v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
199 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
200 writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB);
204 void __init arch_init_irq(void)
206 extern void tx4927_irq_init(void);
209 toshiba_rbtx4927_irq_ioc_init();
210 #ifdef CONFIG_TOSHIBA_FPCIB0
211 if (tx4927_using_backplane)
214 /* Onboard 10M Ether: High Active */
215 set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH);