2 * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc.
4 * Based on linux/arch/mips/pci/ops-tx4938.c,
5 * linux/arch/mips/pci/fixup-rbtx4938.c,
6 * linux/arch/mips/txx9/rbtx4938/setup.c,
7 * and RBTX49xx patch from CELF patch archive.
9 * 2003-2005 (c) MontaVista Software, Inc.
10 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
11 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
18 #include <linux/kernel.h>
19 #include <asm/txx9/tx4927pcic.h>
22 struct pci_controller *channel;
23 struct tx4927_pcic_reg __iomem *pcicptr;
24 } pcicptrs[2]; /* TX4938 has 2 pcic */
26 static void __init set_tx4927_pcicptr(struct pci_controller *channel,
27 struct tx4927_pcic_reg __iomem *pcicptr)
31 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
32 if (pcicptrs[i].channel == channel) {
33 pcicptrs[i].pcicptr = pcicptr;
37 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
38 if (!pcicptrs[i].channel) {
39 pcicptrs[i].channel = channel;
40 pcicptrs[i].pcicptr = pcicptr;
47 struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
48 struct pci_controller *channel)
52 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
53 if (pcicptrs[i].channel == channel)
54 return pcicptrs[i].pcicptr;
59 static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where,
60 struct tx4927_pcic_reg __iomem *pcicptr)
62 if (bus->parent == NULL &&
63 devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0))
65 __raw_writel(((bus->number & 0xff) << 0x10)
66 | ((devfn & 0xff) << 0x08) | (where & 0xfc)
67 | (bus->parent ? 1 : 0),
68 &pcicptr->g2pcfgadrs);
69 /* clear M_ABORT and Disable M_ABORT Int. */
70 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
71 | (PCI_STATUS_REC_MASTER_ABORT << 16),
76 static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr)
78 int code = PCIBIOS_SUCCESSFUL;
80 /* wait write cycle completion before checking error status */
81 while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB)
83 if (__raw_readl(&pcicptr->pcistatus)
84 & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
85 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
86 | (PCI_STATUS_REC_MASTER_ABORT << 16),
88 /* flush write buffer */
90 code = PCIBIOS_DEVICE_NOT_FOUND;
95 static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
100 return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset);
102 static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
107 return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset);
109 static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr)
111 return __raw_readl(&pcicptr->g2pcfgdata);
113 static void icd_writeb(u8 val, int offset,
114 struct tx4927_pcic_reg __iomem *pcicptr)
119 __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
121 static void icd_writew(u16 val, int offset,
122 struct tx4927_pcic_reg __iomem *pcicptr)
127 __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
129 static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr)
131 __raw_writel(val, &pcicptr->g2pcfgdata);
134 static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus)
136 struct pci_controller *channel = bus->sysdata;
137 return get_tx4927_pcicptr(channel);
140 static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn,
141 int where, int size, u32 *val)
143 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
145 if (mkaddr(bus, devfn, where, pcicptr)) {
151 *val = icd_readb(where & 3, pcicptr);
154 *val = icd_readw(where & 3, pcicptr);
157 *val = icd_readl(pcicptr);
159 return check_abort(pcicptr);
162 static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn,
163 int where, int size, u32 val)
165 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
167 if (mkaddr(bus, devfn, where, pcicptr))
171 icd_writeb(val, where & 3, pcicptr);
174 icd_writew(val, where & 3, pcicptr);
177 icd_writel(val, pcicptr);
179 return check_abort(pcicptr);
182 static struct pci_ops tx4927_pci_ops = {
183 .read = tx4927_pci_config_read,
184 .write = tx4927_pci_config_write,
191 } tx4927_pci_opts __devinitdata = {
194 .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */
197 char *__devinit tx4927_pcibios_setup(char *str)
201 if (!strncmp(str, "trdyto=", 7)) {
202 if (strict_strtoul(str + 7, 0, &val) == 0)
203 tx4927_pci_opts.trdyto = val;
206 if (!strncmp(str, "retryto=", 8)) {
207 if (strict_strtoul(str + 8, 0, &val) == 0)
208 tx4927_pci_opts.retryto = val;
211 if (!strncmp(str, "gbwc=", 5)) {
212 if (strict_strtoul(str + 5, 0, &val) == 0)
213 tx4927_pci_opts.gbwc = val;
219 void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
220 struct pci_controller *channel, int extarb)
225 set_tx4927_pcicptr(channel, pcicptr);
227 if (!channel->pci_ops)
229 "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
230 __raw_readl(&pcicptr->pciid) >> 16,
231 __raw_readl(&pcicptr->pciid) & 0xffff,
232 __raw_readl(&pcicptr->pciccrev) & 0xff,
233 extarb ? "External" : "Internal");
234 channel->pci_ops = &tx4927_pci_ops;
236 local_irq_save(flags);
238 /* Disable All Initiator Space */
239 __raw_writel(__raw_readl(&pcicptr->pciccfg)
240 & ~(TX4927_PCIC_PCICCFG_G2PMEN(0)
241 | TX4927_PCIC_PCICCFG_G2PMEN(1)
242 | TX4927_PCIC_PCICCFG_G2PMEN(2)
243 | TX4927_PCIC_PCICCFG_G2PIOEN),
246 /* GB->PCI mappings */
247 __raw_writel((channel->io_resource->end - channel->io_resource->start)
249 &pcicptr->g2piomask);
250 ____raw_writeq((channel->io_resource->start +
251 channel->io_map_base - IO_BASE) |
253 TX4927_PCIC_G2PIOGBASE_ECHG
255 TX4927_PCIC_G2PIOGBASE_BSDIS
257 , &pcicptr->g2piogbase);
258 ____raw_writeq(channel->io_resource->start - channel->io_offset,
259 &pcicptr->g2piopbase);
260 for (i = 0; i < 3; i++) {
261 __raw_writel(0, &pcicptr->g2pmmask[i]);
262 ____raw_writeq(0, &pcicptr->g2pmgbase[i]);
263 ____raw_writeq(0, &pcicptr->g2pmpbase[i]);
265 if (channel->mem_resource->end) {
266 __raw_writel((channel->mem_resource->end
267 - channel->mem_resource->start) >> 4,
268 &pcicptr->g2pmmask[0]);
269 ____raw_writeq(channel->mem_resource->start |
271 TX4927_PCIC_G2PMnGBASE_ECHG
273 TX4927_PCIC_G2PMnGBASE_BSDIS
275 , &pcicptr->g2pmgbase[0]);
276 ____raw_writeq(channel->mem_resource->start -
278 &pcicptr->g2pmpbase[0]);
280 /* PCI->GB mappings (I/O 256B) */
281 __raw_writel(0, &pcicptr->p2giopbase); /* 256B */
282 ____raw_writeq(0, &pcicptr->p2giogbase);
283 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
284 __raw_writel(0, &pcicptr->p2gm0plbase);
285 __raw_writel(0, &pcicptr->p2gm0pubase);
286 ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN |
288 TX4927_PCIC_P2GMnGBASE_TECHG
290 TX4927_PCIC_P2GMnGBASE_TBSDIS
292 , &pcicptr->p2gmgbase[0]);
293 /* PCI->GB mappings (MEM 16MB) */
294 __raw_writel(0xffffffff, &pcicptr->p2gm1plbase);
295 __raw_writel(0xffffffff, &pcicptr->p2gm1pubase);
296 ____raw_writeq(0, &pcicptr->p2gmgbase[1]);
297 /* PCI->GB mappings (MEM 1MB) */
298 __raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */
299 ____raw_writeq(0, &pcicptr->p2gmgbase[2]);
301 /* Clear all (including IRBER) except for GBWC */
302 __raw_writel((tx4927_pci_opts.gbwc << 16)
303 & TX4927_PCIC_PCICCFG_GBWC_MASK,
305 /* Enable Initiator Memory Space */
306 if (channel->mem_resource->end)
307 __raw_writel(__raw_readl(&pcicptr->pciccfg)
308 | TX4927_PCIC_PCICCFG_G2PMEN(0),
310 /* Enable Initiator I/O Space */
311 if (channel->io_resource->end)
312 __raw_writel(__raw_readl(&pcicptr->pciccfg)
313 | TX4927_PCIC_PCICCFG_G2PIOEN,
315 /* Enable Initiator Config */
316 __raw_writel(__raw_readl(&pcicptr->pciccfg)
317 | TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR,
320 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
321 __raw_writel(0, &pcicptr->pcicfg1);
323 __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff)
324 | (tx4927_pci_opts.trdyto & 0xff)
325 | ((tx4927_pci_opts.retryto & 0xff) << 8),
328 /* Clear All Local Bus Status */
329 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
330 /* Enable All Local Bus Interrupts */
331 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask);
332 /* Clear All Initiator Status */
333 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
334 /* Enable All Initiator Interrupts */
335 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask);
336 /* Clear All PCI Status Error */
337 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
338 | (TX4927_PCIC_PCISTATUS_ALL << 16),
339 &pcicptr->pcistatus);
340 /* Enable All PCI Status Error Interrupts */
341 __raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask);
344 /* Reset Bus Arbiter */
345 __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
346 __raw_writel(0, &pcicptr->pbabm);
347 /* Enable Bus Arbiter */
348 __raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg);
351 __raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
352 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
353 &pcicptr->pcistatus);
354 local_irq_restore(flags);
357 "PCI: COMMAND=%04x,PCIMASK=%04x,"
358 "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n",
359 __raw_readl(&pcicptr->pcistatus) & 0xffff,
360 __raw_readl(&pcicptr->pcimask) & 0xffff,
361 __raw_readl(&pcicptr->g2ptocnt) & 0xff,
362 (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8,
363 (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff);
366 static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr)
368 __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16);
369 __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus);
370 __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus);
375 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
376 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
377 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
378 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
379 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
380 { PCI_STATUS_PARITY, "MasterParityError" },
382 { TX4927_PCIC_G2PSTATUS_TTOE, "TIOE" },
383 { TX4927_PCIC_G2PSTATUS_RTOE, "RTOE" },
384 }, pcicstat_tbl[] = {
385 { TX4927_PCIC_PCICSTATUS_PME, "PME" },
386 { TX4927_PCIC_PCICSTATUS_TLB, "TLB" },
387 { TX4927_PCIC_PCICSTATUS_NIB, "NIB" },
388 { TX4927_PCIC_PCICSTATUS_ZIB, "ZIB" },
389 { TX4927_PCIC_PCICSTATUS_PERR, "PERR" },
390 { TX4927_PCIC_PCICSTATUS_SERR, "SERR" },
391 { TX4927_PCIC_PCICSTATUS_GBE, "GBE" },
392 { TX4927_PCIC_PCICSTATUS_IWB, "IWB" },
397 if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) {
398 printk(KERN_CONT "pcistat:%04x(", pcistatus);
399 for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
400 if (pcistatus & pcistat_tbl[i].flag)
401 printk(KERN_CONT "%s%s",
402 cont++ ? " " : "", pcistat_tbl[i].str);
403 printk(KERN_CONT ") ");
405 if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) {
406 printk(KERN_CONT "g2pstatus:%08x(", g2pstatus);
407 for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
408 if (g2pstatus & g2pstat_tbl[i].flag)
409 printk(KERN_CONT "%s%s",
410 cont++ ? " " : "", g2pstat_tbl[i].str);
411 printk(KERN_CONT ") ");
413 if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) {
414 printk(KERN_CONT "pcicstatus:%08x(", pcicstatus);
415 for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
416 if (pcicstatus & pcicstat_tbl[i].flag)
417 printk(KERN_CONT "%s%s",
418 cont++ ? " " : "", pcicstat_tbl[i].str);
419 printk(KERN_CONT ")");
421 printk(KERN_CONT "\n");
424 void tx4927_report_pcic_status(void)
428 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
429 if (pcicptrs[i].pcicptr)
430 tx4927_report_pcic_status1(pcicptrs[i].pcicptr);
434 #ifdef CONFIG_TOSHIBA_FPCIB0
435 static void __init tx4927_quirk_slc90e66_bridge(struct pci_dev *dev)
437 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus);
441 if (__raw_readl(&pcicptr->pbacfg) & TX4927_PCIC_PBACFG_PBAEN) {
442 /* Reset Bus Arbiter */
443 __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
445 * swap reqBP and reqXP (raise priority of SLC90E66).
446 * SLC90E66(PCI-ISA bridge) is connected to REQ2 on
447 * PCI Backplane board.
449 __raw_writel(0x72543610, &pcicptr->pbareqport);
450 __raw_writel(0, &pcicptr->pbabm);
451 /* Use Fixed ParkMaster (required by SLC90E66) */
452 __raw_writel(TX4927_PCIC_PBACFG_FIXPA, &pcicptr->pbacfg);
453 /* Enable Bus Arbiter */
454 __raw_writel(TX4927_PCIC_PBACFG_FIXPA |
455 TX4927_PCIC_PBACFG_PBAEN,
457 printk(KERN_INFO "PCI: Use Fixed Park Master (REQPORT %08x)\n",
458 __raw_readl(&pcicptr->pbareqport));
461 #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
462 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
463 tx4927_quirk_slc90e66_bridge);