2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
6 * Copyright (C) 2000-2001 Toshiba Corporation
7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
9 * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
11 * Define the pci_ops for TX3927.
13 * Much of the code is derived from the original DDB5074 port by
14 * Geert Uytterhoeven <geert@sonycom.com>
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 #include <linux/types.h>
37 #include <linux/pci.h>
38 #include <linux/kernel.h>
39 #include <linux/init.h>
41 #include <asm/addrspace.h>
42 #include <asm/txx9/tx3927.h>
44 static int mkaddr(struct pci_bus *bus, unsigned char devfn, unsigned char where)
46 if (bus->parent == NULL &&
47 devfn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0))
50 ((bus->number & 0xff) << 0x10) |
51 ((devfn & 0xff) << 0x08) |
52 (where & 0xfc) | (bus->parent ? 1 : 0);
54 /* clear M_ABORT and Disable M_ABORT Int. */
55 tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
56 tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT;
60 static inline int check_abort(void)
62 if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT) {
63 tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
64 tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
65 /* flush write buffer */
67 return PCIBIOS_DEVICE_NOT_FOUND;
69 return PCIBIOS_SUCCESSFUL;
72 static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
73 int where, int size, u32 * val)
75 if (mkaddr(bus, devfn, where)) {
77 return PCIBIOS_DEVICE_NOT_FOUND;
82 *val = *(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3));
86 *val = le16_to_cpu(*(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)));
90 *val = le32_to_cpu(tx3927_pcicptr->icd);
97 static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
98 int where, int size, u32 val)
100 if (mkaddr(bus, devfn, where))
101 return PCIBIOS_DEVICE_NOT_FOUND;
105 *(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)) = val;
109 *(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 2)) =
114 tx3927_pcicptr->icd = cpu_to_le32(val);
117 return check_abort();
120 static struct pci_ops tx3927_pci_ops = {
121 .read = tx3927_pci_read_config,
122 .write = tx3927_pci_write_config,
125 void __init tx3927_pcic_setup(struct pci_controller *channel,
126 unsigned long sdram_size, int extarb)
129 unsigned long io_base =
130 channel->io_resource->start + mips_io_port_base - IO_BASE;
131 unsigned long io_size =
132 channel->io_resource->end - channel->io_resource->start;
133 unsigned long io_pciaddr =
134 channel->io_resource->start - channel->io_offset;
135 unsigned long mem_base =
136 channel->mem_resource->start;
137 unsigned long mem_size =
138 channel->mem_resource->end - channel->mem_resource->start;
139 unsigned long mem_pciaddr =
140 channel->mem_resource->start - channel->mem_offset;
142 printk(KERN_INFO "TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s",
143 tx3927_pcicptr->did, tx3927_pcicptr->vid,
145 extarb ? "External" : "Internal");
146 channel->pci_ops = &tx3927_pci_ops;
148 local_irq_save(flags);
149 /* Disable External PCI Config. Access */
150 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
152 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
153 TX3927_PCIC_LBC_TIBSE |
154 TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
156 /* LB->PCI mappings */
157 tx3927_pcicptr->iomas = ~(io_size - 1);
158 tx3927_pcicptr->ilbioma = io_base;
159 tx3927_pcicptr->ipbioma = io_pciaddr;
160 tx3927_pcicptr->mmas = ~(mem_size - 1);
161 tx3927_pcicptr->ilbmma = mem_base;
162 tx3927_pcicptr->ipbmma = mem_pciaddr;
163 /* PCI->LB mappings */
164 tx3927_pcicptr->iobas = 0xffffffff;
165 tx3927_pcicptr->ioba = 0;
166 tx3927_pcicptr->tlbioma = 0;
167 tx3927_pcicptr->mbas = ~(sdram_size - 1);
168 tx3927_pcicptr->mba = 0;
169 tx3927_pcicptr->tlbmma = 0;
170 /* Enable Direct mapping Address Space Decoder */
171 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
173 /* Clear All Local Bus Status */
174 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
175 /* Enable All Local Bus Interrupts */
176 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
177 /* Clear All PCI Status Error */
178 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
179 /* Enable All PCI Status Error Interrupts */
180 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
182 /* PCIC Int => IRC IRQ10 */
183 tx3927_pcicptr->il = TX3927_IR_PCI;
184 /* Target Control (per errata) */
185 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
187 /* Enable Bus Arbiter */
189 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
191 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
194 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
195 local_irq_restore(flags);