arch/mips/mm/c-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
   7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/config.h>
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/sched.h>
  14 #include <linux/mm.h>
  15 #include <linux/bitops.h>
  16
  17 #include <asm/bcache.h>
  18 #include <asm/bootinfo.h>
  19 #include <asm/cache.h>
  20 #include <asm/cacheops.h>
  21 #include <asm/cpu.h>
  22 #include <asm/cpu-features.h>
  23 #include <asm/io.h>
  24 #include <asm/page.h>
  25 #include <asm/pgtable.h>
  26 #include <asm/r4kcache.h>
  27 #include <asm/system.h>
  28 #include <asm/mmu_context.h>
  29 #include <asm/war.h>
  30 #include <asm/cacheflush.h> /* for run_uncached() */
  31
  32 /*
  33  * Must die.
  34  */
  35 static unsigned long icache_size __read_mostly;
  36 static unsigned long dcache_size __read_mostly;
  37 static unsigned long scache_size __read_mostly;
  38
  39 /*
  40  * Dummy cache handling routines for machines without boardcaches
  41  */
  42 static void no_sc_noop(void) {}
  43
  44 static struct bcache_ops no_sc_ops = {
  45         .bc_enable = (void *)no_sc_noop,
  46         .bc_disable = (void *)no_sc_noop,
  47         .bc_wback_inv = (void *)no_sc_noop,
  48         .bc_inv = (void *)no_sc_noop
  49 };
  50
  51 struct bcache_ops *bcops = &no_sc_ops;
  52
  53 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002010)
  54 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002020)
  55
  56 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
  57 do {                                                                    \
  58         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
  59                 *(volatile unsigned long *)CKSEG1;                      \
  60         if (R4600_V1_HIT_CACHEOP_WAR)                                   \
  61                 __asm__ __volatile__("nop;nop;nop;nop");                \
  62 } while (0)
  63
  64 static void (*r4k_blast_dcache_page)(unsigned long addr);
  65
  66 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
  67 {
  68         R4600_HIT_CACHEOP_WAR_IMPL;
  69         blast_dcache32_page(addr);
  70 }
  71
  72 static inline void r4k_blast_dcache_page_setup(void)
  73 {
  74         unsigned long  dc_lsize = cpu_dcache_line_size();
  75
  76         if (dc_lsize == 16)
  77                 r4k_blast_dcache_page = blast_dcache16_page;
  78         else if (dc_lsize == 32)
  79                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
  80 }
  81
  82 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
  83
  84 static inline void r4k_blast_dcache_page_indexed_setup(void)
  85 {
  86         unsigned long dc_lsize = cpu_dcache_line_size();
  87
  88         if (dc_lsize == 16)
  89                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
  90         else if (dc_lsize == 32)
  91                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
  92 }
  93
  94 static void (* r4k_blast_dcache)(void);
  95
  96 static inline void r4k_blast_dcache_setup(void)
  97 {
  98         unsigned long dc_lsize = cpu_dcache_line_size();
  99
 100         if (dc_lsize == 16)
 101                 r4k_blast_dcache = blast_dcache16;
 102         else if (dc_lsize == 32)
 103                 r4k_blast_dcache = blast_dcache32;
 104 }
 105
 106 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
 107 #define JUMP_TO_ALIGN(order) \
 108         __asm__ __volatile__( \
 109                 "b\t1f\n\t" \
 110                 ".align\t" #order "\n\t" \
 111                 "1:\n\t" \
 112                 )
 113 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
 114 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
 115
 116 static inline void blast_r4600_v1_icache32(void)
 117 {
 118         unsigned long flags;
 119
 120         local_irq_save(flags);
 121         blast_icache32();
 122         local_irq_restore(flags);
 123 }
 124
 125 static inline void tx49_blast_icache32(void)
 126 {
 127         unsigned long start = INDEX_BASE;
 128         unsigned long end = start + current_cpu_data.icache.waysize;
 129         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 130         unsigned long ws_end = current_cpu_data.icache.ways <<
 131                                current_cpu_data.icache.waybit;
 132         unsigned long ws, addr;
 133
 134         CACHE32_UNROLL32_ALIGN2;
 135         /* I'm in even chunk.  blast odd chunks */
 136         for (ws = 0; ws < ws_end; ws += ws_inc)
 137                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 138                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 139         CACHE32_UNROLL32_ALIGN;
 140         /* I'm in odd chunk.  blast even chunks */
 141         for (ws = 0; ws < ws_end; ws += ws_inc)
 142                 for (addr = start; addr < end; addr += 0x400 * 2)
 143                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 144 }
 145
 146 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 147 {
 148         unsigned long flags;
 149
 150         local_irq_save(flags);
 151         blast_icache32_page_indexed(page);
 152         local_irq_restore(flags);
 153 }
 154
 155 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 156 {
 157         unsigned long start = page;
 158         unsigned long end = start + PAGE_SIZE;
 159         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 160         unsigned long ws_end = current_cpu_data.icache.ways <<
 161                                current_cpu_data.icache.waybit;
 162         unsigned long ws, addr;
 163
 164         CACHE32_UNROLL32_ALIGN2;
 165         /* I'm in even chunk.  blast odd chunks */
 166         for (ws = 0; ws < ws_end; ws += ws_inc)
 167                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 168                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 169         CACHE32_UNROLL32_ALIGN;
 170         /* I'm in odd chunk.  blast even chunks */
 171         for (ws = 0; ws < ws_end; ws += ws_inc)
 172                 for (addr = start; addr < end; addr += 0x400 * 2)
 173                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 174 }
 175
 176 static void (* r4k_blast_icache_page)(unsigned long addr);
 177
 178 static inline void r4k_blast_icache_page_setup(void)
 179 {
 180         unsigned long ic_lsize = cpu_icache_line_size();
 181
 182         if (ic_lsize == 16)
 183                 r4k_blast_icache_page = blast_icache16_page;
 184         else if (ic_lsize == 32)
 185                 r4k_blast_icache_page = blast_icache32_page;
 186         else if (ic_lsize == 64)
 187                 r4k_blast_icache_page = blast_icache64_page;
 188 }
 189
 190
 191 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
 192
 193 static inline void r4k_blast_icache_page_indexed_setup(void)
 194 {
 195         unsigned long ic_lsize = cpu_icache_line_size();
 196
 197         if (ic_lsize == 16)
 198                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
 199         else if (ic_lsize == 32) {
 200                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 201                         r4k_blast_icache_page_indexed =
 202                                 blast_icache32_r4600_v1_page_indexed;
 203                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 204                         r4k_blast_icache_page_indexed =
 205                                 tx49_blast_icache32_page_indexed;
 206                 else
 207                         r4k_blast_icache_page_indexed =
 208                                 blast_icache32_page_indexed;
 209         } else if (ic_lsize == 64)
 210                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
 211 }
 212
 213 static void (* r4k_blast_icache)(void);
 214
 215 static inline void r4k_blast_icache_setup(void)
 216 {
 217         unsigned long ic_lsize = cpu_icache_line_size();
 218
 219         if (ic_lsize == 16)
 220                 r4k_blast_icache = blast_icache16;
 221         else if (ic_lsize == 32) {
 222                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 223                         r4k_blast_icache = blast_r4600_v1_icache32;
 224                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 225                         r4k_blast_icache = tx49_blast_icache32;
 226                 else
 227                         r4k_blast_icache = blast_icache32;
 228         } else if (ic_lsize == 64)
 229                 r4k_blast_icache = blast_icache64;
 230 }
 231
 232 static void (* r4k_blast_scache_page)(unsigned long addr);
 233
 234 static inline void r4k_blast_scache_page_setup(void)
 235 {
 236         unsigned long sc_lsize = cpu_scache_line_size();
 237
 238         if (sc_lsize == 16)
 239                 r4k_blast_scache_page = blast_scache16_page;
 240         else if (sc_lsize == 32)
 241                 r4k_blast_scache_page = blast_scache32_page;
 242         else if (sc_lsize == 64)
 243                 r4k_blast_scache_page = blast_scache64_page;
 244         else if (sc_lsize == 128)
 245                 r4k_blast_scache_page = blast_scache128_page;
 246 }
 247
 248 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
 249
 250 static inline void r4k_blast_scache_page_indexed_setup(void)
 251 {
 252         unsigned long sc_lsize = cpu_scache_line_size();
 253
 254         if (sc_lsize == 16)
 255                 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
 256         else if (sc_lsize == 32)
 257                 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
 258         else if (sc_lsize == 64)
 259                 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
 260         else if (sc_lsize == 128)
 261                 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
 262 }
 263
 264 static void (* r4k_blast_scache)(void);
 265
 266 static inline void r4k_blast_scache_setup(void)
 267 {
 268         unsigned long sc_lsize = cpu_scache_line_size();
 269
 270         if (sc_lsize == 16)
 271                 r4k_blast_scache = blast_scache16;
 272         else if (sc_lsize == 32)
 273                 r4k_blast_scache = blast_scache32;
 274         else if (sc_lsize == 64)
 275                 r4k_blast_scache = blast_scache64;
 276         else if (sc_lsize == 128)
 277                 r4k_blast_scache = blast_scache128;
 278 }
 279
 280 /*
 281  * This is former mm's flush_cache_all() which really should be
 282  * flush_cache_vunmap these days ...
 283  */
 284 static inline void local_r4k_flush_cache_all(void * args)
 285 {
 286         r4k_blast_dcache();
 287         r4k_blast_icache();
 288 }
 289
 290 static void r4k_flush_cache_all(void)
 291 {
 292         if (!cpu_has_dc_aliases)
 293                 return;
 294
 295         on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
 296 }
 297
 298 static inline void local_r4k___flush_cache_all(void * args)
 299 {
 300         r4k_blast_dcache();
 301         r4k_blast_icache();
 302
 303         switch (current_cpu_data.cputype) {
 304         case CPU_R4000SC:
 305         case CPU_R4000MC:
 306         case CPU_R4400SC:
 307         case CPU_R4400MC:
 308         case CPU_R10000:
 309         case CPU_R12000:
 310                 r4k_blast_scache();
 311         }
 312 }
 313
 314 static void r4k___flush_cache_all(void)
 315 {
 316         on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1);
 317 }
 318
 319 static inline void local_r4k_flush_cache_range(void * args)
 320 {
 321         struct vm_area_struct *vma = args;
 322         int exec;
 323
 324         if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
 325                 return;
 326
 327         exec = vma->vm_flags & VM_EXEC;
 328         if (cpu_has_dc_aliases || exec)
 329                 r4k_blast_dcache();
 330         if (exec)
 331                 r4k_blast_icache();
 332 }
 333
 334 static void r4k_flush_cache_range(struct vm_area_struct *vma,
 335         unsigned long start, unsigned long end)
 336 {
 337         on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
 338 }
 339
 340 static inline void local_r4k_flush_cache_mm(void * args)
 341 {
 342         struct mm_struct *mm = args;
 343
 344         if (!cpu_context(smp_processor_id(), mm))
 345                 return;
 346
 347         r4k_blast_dcache();
 348         r4k_blast_icache();
 349
 350         /*
 351          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
 352          * only flush the primary caches but R10000 and R12000 behave sane ...
 353          */
 354         if (current_cpu_data.cputype == CPU_R4000SC ||
 355             current_cpu_data.cputype == CPU_R4000MC ||
 356             current_cpu_data.cputype == CPU_R4400SC ||
 357             current_cpu_data.cputype == CPU_R4400MC)
 358                 r4k_blast_scache();
 359 }
 360
 361 static void r4k_flush_cache_mm(struct mm_struct *mm)
 362 {
 363         if (!cpu_has_dc_aliases)
 364                 return;
 365
 366         on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
 367 }
 368
 369 struct flush_cache_page_args {
 370         struct vm_area_struct *vma;
 371         unsigned long addr;
 372 };
 373
 374 static inline void local_r4k_flush_cache_page(void *args)
 375 {
 376         struct flush_cache_page_args *fcp_args = args;
 377         struct vm_area_struct *vma = fcp_args->vma;
 378         unsigned long addr = fcp_args->addr;
 379         int exec = vma->vm_flags & VM_EXEC;
 380         struct mm_struct *mm = vma->vm_mm;
 381         pgd_t *pgdp;
 382         pud_t *pudp;
 383         pmd_t *pmdp;
 384         pte_t *ptep;
 385
 386         /*
 387          * If ownes no valid ASID yet, cannot possibly have gotten
 388          * this page into the cache.
 389          */
 390         if (cpu_context(smp_processor_id(), mm) == 0)
 391                 return;
 392
 393         addr &= PAGE_MASK;
 394         pgdp = pgd_offset(mm, addr);
 395         pudp = pud_offset(pgdp, addr);
 396         pmdp = pmd_offset(pudp, addr);
 397         ptep = pte_offset(pmdp, addr);
 398
 399         /*
 400          * If the page isn't marked valid, the page cannot possibly be
 401          * in the cache.
 402          */
 403         if (!(pte_val(*ptep) & _PAGE_PRESENT))
 404                 return;
 405
 406         /*
 407          * Doing flushes for another ASID than the current one is
 408          * too difficult since stupid R4k caches do a TLB translation
 409          * for every cache flush operation.  So we do indexed flushes
 410          * in that case, which doesn't overly flush the cache too much.
 411          */
 412         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
 413                 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 414                         r4k_blast_dcache_page(addr);
 415                         if (exec && !cpu_icache_snoops_remote_store)
 416                                 r4k_blast_scache_page(addr);
 417                 }
 418                 if (exec)
 419                         r4k_blast_icache_page(addr);
 420
 421                 return;
 422         }
 423
 424         /*
 425          * Do indexed flush, too much work to get the (possible) TLB refills
 426          * to work correctly.
 427          */
 428         addr = INDEX_BASE + (addr & (dcache_size - 1));
 429         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 430                 r4k_blast_dcache_page_indexed(addr);
 431                 if (exec && !cpu_icache_snoops_remote_store)
 432                         r4k_blast_scache_page_indexed(addr);
 433         }
 434         if (exec) {
 435                 if (cpu_has_vtag_icache) {
 436                         int cpu = smp_processor_id();
 437
 438                         if (cpu_context(cpu, mm) != 0)
 439                                 drop_mmu_context(mm, cpu);
 440                 } else
 441                         r4k_blast_icache_page_indexed(addr);
 442         }
 443 }
 444
 445 static void r4k_flush_cache_page(struct vm_area_struct *vma,
 446         unsigned long addr, unsigned long pfn)
 447 {
 448         struct flush_cache_page_args args;
 449
 450         args.vma = vma;
 451         args.addr = addr;
 452
 453         on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
 454 }
 455
 456 static inline void local_r4k_flush_data_cache_page(void * addr)
 457 {
 458         r4k_blast_dcache_page((unsigned long) addr);
 459 }
 460
 461 static void r4k_flush_data_cache_page(unsigned long addr)
 462 {
 463         on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);
 464 }
 465
 466 struct flush_icache_range_args {
 467         unsigned long start;
 468         unsigned long end;
 469 };
 470
 471 static inline void local_r4k_flush_icache_range(void *args)
 472 {
 473         struct flush_icache_range_args *fir_args = args;
 474         unsigned long start = fir_args->start;
 475         unsigned long end = fir_args->end;
 476
 477         if (!cpu_has_ic_fills_f_dc) {
 478                 if (end - start > dcache_size) {
 479                         r4k_blast_dcache();
 480                 } else {
 481                         R4600_HIT_CACHEOP_WAR_IMPL;
 482                         protected_blast_dcache_range(start, end);
 483                 }
 484
 485                 if (!cpu_icache_snoops_remote_store) {
 486                         if (end - start > scache_size)
 487                                 r4k_blast_scache();
 488                         else
 489                                 protected_blast_scache_range(start, end);
 490                 }
 491         }
 492
 493         if (end - start > icache_size)
 494                 r4k_blast_icache();
 495         else
 496                 protected_blast_icache_range(start, end);
 497 }
 498
 499 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
 500 {
 501         struct flush_icache_range_args args;
 502
 503         args.start = start;
 504         args.end = end;
 505
 506         on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
 507         instruction_hazard();
 508 }
 509
 510 /*
 511  * Ok, this seriously sucks.  We use them to flush a user page but don't
 512  * know the virtual address, so we have to blast away the whole icache
 513  * which is significantly more expensive than the real thing.  Otoh we at
 514  * least know the kernel address of the page so we can flush it
 515  * selectivly.
 516  */
 517
 518 struct flush_icache_page_args {
 519         struct vm_area_struct *vma;
 520         struct page *page;
 521 };
 522
 523 static inline void local_r4k_flush_icache_page(void *args)
 524 {
 525         struct flush_icache_page_args *fip_args = args;
 526         struct vm_area_struct *vma = fip_args->vma;
 527         struct page *page = fip_args->page;
 528
 529         /*
 530          * Tricky ...  Because we don't know the virtual address we've got the
 531          * choice of either invalidating the entire primary and secondary
 532          * caches or invalidating the secondary caches also.  With the subset
 533          * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the
 534          * secondary cache will result in any entries in the primary caches
 535          * also getting invalidated which hopefully is a bit more economical.
 536          */
 537         if (cpu_has_subset_pcaches) {
 538                 unsigned long addr = (unsigned long) page_address(page);
 539
 540                 r4k_blast_scache_page(addr);
 541                 ClearPageDcacheDirty(page);
 542
 543                 return;
 544         }
 545
 546         if (!cpu_has_ic_fills_f_dc) {
 547                 unsigned long addr = (unsigned long) page_address(page);
 548                 r4k_blast_dcache_page(addr);
 549                 if (!cpu_icache_snoops_remote_store)
 550                         r4k_blast_scache_page(addr);
 551                 ClearPageDcacheDirty(page);
 552         }
 553
 554         /*
 555          * We're not sure of the virtual address(es) involved here, so
 556          * we have to flush the entire I-cache.
 557          */
 558         if (cpu_has_vtag_icache) {
 559                 int cpu = smp_processor_id();
 560
 561                 if (cpu_context(cpu, vma->vm_mm) != 0)
 562                         drop_mmu_context(vma->vm_mm, cpu);
 563         } else
 564                 r4k_blast_icache();
 565 }
 566
 567 static void r4k_flush_icache_page(struct vm_area_struct *vma,
 568         struct page *page)
 569 {
 570         struct flush_icache_page_args args;
 571
 572         /*
 573          * If there's no context yet, or the page isn't executable, no I-cache
 574          * flush is needed.
 575          */
 576         if (!(vma->vm_flags & VM_EXEC))
 577                 return;
 578
 579         args.vma = vma;
 580         args.page = page;
 581
 582         on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1);
 583 }
 584
 585
 586 #ifdef CONFIG_DMA_NONCOHERENT
 587
 588 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 589 {
 590         /* Catch bad driver code */
 591         BUG_ON(size == 0);
 592
 593         if (cpu_has_subset_pcaches) {
 594                 if (size >= scache_size)
 595                         r4k_blast_scache();
 596                 else
 597                         blast_scache_range(addr, addr + size);
 598                 return;
 599         }
 600
 601         /*
 602          * Either no secondary cache or the available caches don't have the
 603          * subset property so we have to flush the primary caches
 604          * explicitly
 605          */
 606         if (size >= dcache_size) {
 607                 r4k_blast_dcache();
 608         } else {
 609                 R4600_HIT_CACHEOP_WAR_IMPL;
 610                 blast_dcache_range(addr, addr + size);
 611         }
 612
 613         bc_wback_inv(addr, size);
 614 }
 615
 616 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 617 {
 618         /* Catch bad driver code */
 619         BUG_ON(size == 0);
 620
 621         if (cpu_has_subset_pcaches) {
 622                 if (size >= scache_size)
 623                         r4k_blast_scache();
 624                 else
 625                         blast_scache_range(addr, addr + size);
 626                 return;
 627         }
 628
 629         if (size >= dcache_size) {
 630                 r4k_blast_dcache();
 631         } else {
 632                 R4600_HIT_CACHEOP_WAR_IMPL;
 633                 blast_dcache_range(addr, addr + size);
 634         }
 635
 636         bc_inv(addr, size);
 637 }
 638 #endif /* CONFIG_DMA_NONCOHERENT */
 639
 640 /*
 641  * While we're protected against bad userland addresses we don't care
 642  * very much about what happens in that case.  Usually a segmentation
 643  * fault will dump the process later on anyway ...
 644  */
 645 static void local_r4k_flush_cache_sigtramp(void * arg)
 646 {
 647         unsigned long ic_lsize = cpu_icache_line_size();
 648         unsigned long dc_lsize = cpu_dcache_line_size();
 649         unsigned long sc_lsize = cpu_scache_line_size();
 650         unsigned long addr = (unsigned long) arg;
 651
 652         R4600_HIT_CACHEOP_WAR_IMPL;
 653         protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
 654         if (!cpu_icache_snoops_remote_store)
 655                 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
 656         protected_flush_icache_line(addr & ~(ic_lsize - 1));
 657         if (MIPS4K_ICACHE_REFILL_WAR) {
 658                 __asm__ __volatile__ (
 659                         ".set push\n\t"
 660                         ".set noat\n\t"
 661                         ".set mips3\n\t"
 662 #ifdef CONFIG_32BIT
 663                         "la     $at,1f\n\t"
 664 #endif
 665 #ifdef CONFIG_64BIT
 666                         "dla    $at,1f\n\t"
 667 #endif
 668                         "cache  %0,($at)\n\t"
 669                         "nop; nop; nop\n"
 670                         "1:\n\t"
 671                         ".set pop"
 672                         :
 673                         : "i" (Hit_Invalidate_I));
 674         }
 675         if (MIPS_CACHE_SYNC_WAR)
 676                 __asm__ __volatile__ ("sync");
 677 }
 678
 679 static void r4k_flush_cache_sigtramp(unsigned long addr)
 680 {
 681         on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1);
 682 }
 683
 684 static void r4k_flush_icache_all(void)
 685 {
 686         if (cpu_has_vtag_icache)
 687                 r4k_blast_icache();
 688 }
 689
 690 static inline void rm7k_erratum31(void)
 691 {
 692         const unsigned long ic_lsize = 32;
 693         unsigned long addr;
 694
 695         /* RM7000 erratum #31. The icache is screwed at startup. */
 696         write_c0_taglo(0);
 697         write_c0_taghi(0);
 698
 699         for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
 700                 __asm__ __volatile__ (
 701                         ".set push\n\t"
 702                         ".set noreorder\n\t"
 703                         ".set mips3\n\t"
 704                         "cache\t%1, 0(%0)\n\t"
 705                         "cache\t%1, 0x1000(%0)\n\t"
 706                         "cache\t%1, 0x2000(%0)\n\t"
 707                         "cache\t%1, 0x3000(%0)\n\t"
 708                         "cache\t%2, 0(%0)\n\t"
 709                         "cache\t%2, 0x1000(%0)\n\t"
 710                         "cache\t%2, 0x2000(%0)\n\t"
 711                         "cache\t%2, 0x3000(%0)\n\t"
 712                         "cache\t%1, 0(%0)\n\t"
 713                         "cache\t%1, 0x1000(%0)\n\t"
 714                         "cache\t%1, 0x2000(%0)\n\t"
 715                         "cache\t%1, 0x3000(%0)\n\t"
 716                         ".set pop\n"
 717                         :
 718                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
 719         }
 720 }
 721
 722 static char *way_string[] __initdata = { NULL, "direct mapped", "2-way",
 723         "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
 724 };
 725
 726 static void __init probe_pcache(void)
 727 {
 728         struct cpuinfo_mips *c = &current_cpu_data;
 729         unsigned int config = read_c0_config();
 730         unsigned int prid = read_c0_prid();
 731         unsigned long config1;
 732         unsigned int lsize;
 733
 734         switch (c->cputype) {
 735         case CPU_R4600:                 /* QED style two way caches? */
 736         case CPU_R4700:
 737         case CPU_R5000:
 738         case CPU_NEVADA:
 739                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 740                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 741                 c->icache.ways = 2;
 742                 c->icache.waybit = ffs(icache_size/2) - 1;
 743
 744                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 745                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 746                 c->dcache.ways = 2;
 747                 c->dcache.waybit= ffs(dcache_size/2) - 1;
 748
 749                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 750                 break;
 751
 752         case CPU_R5432:
 753         case CPU_R5500:
 754                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 755                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 756                 c->icache.ways = 2;
 757                 c->icache.waybit= 0;
 758
 759                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 760                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 761                 c->dcache.ways = 2;
 762                 c->dcache.waybit = 0;
 763
 764                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 765                 break;
 766
 767         case CPU_TX49XX:
 768                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 769                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 770                 c->icache.ways = 4;
 771                 c->icache.waybit= 0;
 772
 773                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 774                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 775                 c->dcache.ways = 4;
 776                 c->dcache.waybit = 0;
 777
 778                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 779                 break;
 780
 781         case CPU_R4000PC:
 782         case CPU_R4000SC:
 783         case CPU_R4000MC:
 784         case CPU_R4400PC:
 785         case CPU_R4400SC:
 786         case CPU_R4400MC:
 787         case CPU_R4300:
 788                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 789                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 790                 c->icache.ways = 1;
 791                 c->icache.waybit = 0;   /* doesn't matter */
 792
 793                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 794                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 795                 c->dcache.ways = 1;
 796                 c->dcache.waybit = 0;   /* does not matter */
 797
 798                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 799                 break;
 800
 801         case CPU_R10000:
 802         case CPU_R12000:
 803                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
 804                 c->icache.linesz = 64;
 805                 c->icache.ways = 2;
 806                 c->icache.waybit = 0;
 807
 808                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
 809                 c->dcache.linesz = 32;
 810                 c->dcache.ways = 2;
 811                 c->dcache.waybit = 0;
 812
 813                 c->options |= MIPS_CPU_PREFETCH;
 814                 break;
 815
 816         case CPU_VR4133:
 817                 write_c0_config(config & ~CONF_EB);
 818         case CPU_VR4131:
 819                 /* Workaround for cache instruction bug of VR4131 */
 820                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
 821                     c->processor_id == 0x0c82U) {
 822                         config &= ~0x00000030U;
 823                         config |= 0x00410000U;
 824                         write_c0_config(config);
 825                 }
 826                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 827                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 828                 c->icache.ways = 2;
 829                 c->icache.waybit = ffs(icache_size/2) - 1;
 830
 831                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 832                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 833                 c->dcache.ways = 2;
 834                 c->dcache.waybit = ffs(dcache_size/2) - 1;
 835
 836                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 837                 break;
 838
 839         case CPU_VR41XX:
 840         case CPU_VR4111:
 841         case CPU_VR4121:
 842         case CPU_VR4122:
 843         case CPU_VR4181:
 844         case CPU_VR4181A:
 845                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 846                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 847                 c->icache.ways = 1;
 848                 c->icache.waybit = 0;   /* doesn't matter */
 849
 850                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 851                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 852                 c->dcache.ways = 1;
 853                 c->dcache.waybit = 0;   /* does not matter */
 854
 855                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 856                 break;
 857
 858         case CPU_RM7000:
 859                 rm7k_erratum31();
 860
 861         case CPU_RM9000:
 862                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 863                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 864                 c->icache.ways = 4;
 865                 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
 866
 867                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 868                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 869                 c->dcache.ways = 4;
 870                 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
 871
 872 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
 873                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 874 #endif
 875                 c->options |= MIPS_CPU_PREFETCH;
 876                 break;
 877
 878         default:
 879                 if (!(config & MIPS_CONF_M))
 880                         panic("Don't know how to probe P-caches on this cpu.");
 881
 882                 /*
 883                  * So we seem to be a MIPS32 or MIPS64 CPU
 884                  * So let's probe the I-cache ...
 885                  */
 886                 config1 = read_c0_config1();
 887
 888                 if ((lsize = ((config1 >> 19) & 7)))
 889                         c->icache.linesz = 2 << lsize;
 890                 else
 891                         c->icache.linesz = lsize;
 892                 c->icache.sets = 64 << ((config1 >> 22) & 7);
 893                 c->icache.ways = 1 + ((config1 >> 16) & 7);
 894
 895                 icache_size = c->icache.sets *
 896                               c->icache.ways *
 897                               c->icache.linesz;
 898                 c->icache.waybit = ffs(icache_size/c->icache.ways) - 1;
 899
 900                 if (config & 0x8)               /* VI bit */
 901                         c->icache.flags |= MIPS_CACHE_VTAG;
 902
 903                 /*
 904                  * Now probe the MIPS32 / MIPS64 data cache.
 905                  */
 906                 c->dcache.flags = 0;
 907
 908                 if ((lsize = ((config1 >> 10) & 7)))
 909                         c->dcache.linesz = 2 << lsize;
 910                 else
 911                         c->dcache.linesz= lsize;
 912                 c->dcache.sets = 64 << ((config1 >> 13) & 7);
 913                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
 914
 915                 dcache_size = c->dcache.sets *
 916                               c->dcache.ways *
 917                               c->dcache.linesz;
 918                 c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1;
 919
 920                 c->options |= MIPS_CPU_PREFETCH;
 921                 break;
 922         }
 923
 924         /*
 925          * Processor configuration sanity check for the R4000SC erratum
 926          * #5.  With page sizes larger than 32kB there is no possibility
 927          * to get a VCE exception anymore so we don't care about this
 928          * misconfiguration.  The case is rather theoretical anyway;
 929          * presumably no vendor is shipping his hardware in the "bad"
 930          * configuration.
 931          */
 932         if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
 933             !(config & CONF_SC) && c->icache.linesz != 16 &&
 934             PAGE_SIZE <= 0x8000)
 935                 panic("Improper R4000SC processor configuration detected");
 936
 937         /* compute a couple of other cache variables */
 938         c->icache.waysize = icache_size / c->icache.ways;
 939         c->dcache.waysize = dcache_size / c->dcache.ways;
 940
 941         c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
 942         c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
 943
 944         /*
 945          * R10000 and R12000 P-caches are odd in a positive way.  They're 32kB
 946          * 2-way virtually indexed so normally would suffer from aliases.  So
 947          * normally they'd suffer from aliases but magic in the hardware deals
 948          * with that for us so we don't need to take care ourselves.
 949          */
 950         switch (c->cputype) {
 951         case CPU_20KC:
 952         case CPU_25KF:
 953         case CPU_R10000:
 954         case CPU_R12000:
 955         case CPU_SB1:
 956                 break;
 957         case CPU_24K:
 958                 if (!(read_c0_config7() & (1 << 16)))
 959         default:
 960                         if (c->dcache.waysize > PAGE_SIZE)
 961                                 c->dcache.flags |= MIPS_CACHE_ALIASES;
 962         }
 963
 964         switch (c->cputype) {
 965         case CPU_20KC:
 966                 /*
 967                  * Some older 20Kc chips doesn't have the 'VI' bit in
 968                  * the config register.
 969                  */
 970                 c->icache.flags |= MIPS_CACHE_VTAG;
 971                 break;
 972
 973         case CPU_AU1000:
 974         case CPU_AU1500:
 975         case CPU_AU1100:
 976         case CPU_AU1550:
 977         case CPU_AU1200:
 978                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
 979                 break;
 980         }
 981
 982         printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
 983                icache_size >> 10,
 984                cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
 985                way_string[c->icache.ways], c->icache.linesz);
 986
 987         printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
 988                dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
 989 }
 990
 991 /*
 992  * If you even _breathe_ on this function, look at the gcc output and make sure
 993  * it does not pop things on and off the stack for the cache sizing loop that
 994  * executes in KSEG1 space or else you will crash and burn badly.  You have
 995  * been warned.
 996  */
 997 static int __init probe_scache(void)
 998 {
 999         extern unsigned long stext;
1000         unsigned long flags, addr, begin, end, pow2;
1001         unsigned int config = read_c0_config();
1002         struct cpuinfo_mips *c = &current_cpu_data;
1003         int tmp;
1004
1005         if (config & CONF_SC)
1006                 return 0;
1007
1008         begin = (unsigned long) &stext;
1009         begin &= ~((4 * 1024 * 1024) - 1);
1010         end = begin + (4 * 1024 * 1024);
1011
1012         /*
1013          * This is such a bitch, you'd think they would make it easy to do
1014          * this.  Away you daemons of stupidity!
1015          */
1016         local_irq_save(flags);
1017
1018         /* Fill each size-multiple cache line with a valid tag. */
1019         pow2 = (64 * 1024);
1020         for (addr = begin; addr < end; addr = (begin + pow2)) {
1021                 unsigned long *p = (unsigned long *) addr;
1022                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1023                 pow2 <<= 1;
1024         }
1025
1026         /* Load first line with zero (therefore invalid) tag. */
1027         write_c0_taglo(0);
1028         write_c0_taghi(0);
1029         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1030         cache_op(Index_Store_Tag_I, begin);
1031         cache_op(Index_Store_Tag_D, begin);
1032         cache_op(Index_Store_Tag_SD, begin);
1033
1034         /* Now search for the wrap around point. */
1035         pow2 = (128 * 1024);
1036         tmp = 0;
1037         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1038                 cache_op(Index_Load_Tag_SD, addr);
1039                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1040                 if (!read_c0_taglo())
1041                         break;
1042                 pow2 <<= 1;
1043         }
1044         local_irq_restore(flags);
1045         addr -= begin;
1046
1047         scache_size = addr;
1048         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1049         c->scache.ways = 1;
1050         c->dcache.waybit = 0;           /* does not matter */
1051
1052         return 1;
1053 }
1054
1055 extern int r5k_sc_init(void);
1056 extern int rm7k_sc_init(void);
1057
1058 static void __init setup_scache(void)
1059 {
1060         struct cpuinfo_mips *c = &current_cpu_data;
1061         unsigned int config = read_c0_config();
1062         int sc_present = 0;
1063
1064         /*
1065          * Do the probing thing on R4000SC and R4400SC processors.  Other
1066          * processors don't have a S-cache that would be relevant to the
1067          * Linux memory managment.
1068          */
1069         switch (c->cputype) {
1070         case CPU_R4000SC:
1071         case CPU_R4000MC:
1072         case CPU_R4400SC:
1073         case CPU_R4400MC:
1074                 sc_present = run_uncached(probe_scache);
1075                 if (sc_present)
1076                         c->options |= MIPS_CPU_CACHE_CDEX_S;
1077                 break;
1078
1079         case CPU_R10000:
1080         case CPU_R12000:
1081                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1082                 c->scache.linesz = 64 << ((config >> 13) & 1);
1083                 c->scache.ways = 2;
1084                 c->scache.waybit= 0;
1085                 sc_present = 1;
1086                 break;
1087
1088         case CPU_R5000:
1089         case CPU_NEVADA:
1090 #ifdef CONFIG_R5000_CPU_SCACHE
1091                 r5k_sc_init();
1092 #endif
1093                 return;
1094
1095         case CPU_RM7000:
1096         case CPU_RM9000:
1097 #ifdef CONFIG_RM7000_CPU_SCACHE
1098                 rm7k_sc_init();
1099 #endif
1100                 return;
1101
1102         default:
1103                 sc_present = 0;
1104         }
1105
1106         if (!sc_present)
1107                 return;
1108
1109         if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
1110              c->isa_level == MIPS_CPU_ISA_M64R1) &&
1111             !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1112                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1113
1114         /* compute a couple of other cache variables */
1115         c->scache.waysize = scache_size / c->scache.ways;
1116
1117         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1118
1119         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1120                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1121
1122         c->options |= MIPS_CPU_SUBSET_CACHES;
1123 }
1124
1125 static inline void coherency_setup(void)
1126 {
1127         change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
1128
1129         /*
1130          * c0_status.cu=0 specifies that updates by the sc instruction use
1131          * the coherency mode specified by the TLB; 1 means cachable
1132          * coherent update on write will be used.  Not all processors have
1133          * this bit and; some wire it to zero, others like Toshiba had the
1134          * silly idea of putting something else there ...
1135          */
1136         switch (current_cpu_data.cputype) {
1137         case CPU_R4000PC:
1138         case CPU_R4000SC:
1139         case CPU_R4000MC:
1140         case CPU_R4400PC:
1141         case CPU_R4400SC:
1142         case CPU_R4400MC:
1143                 clear_c0_config(CONF_CU);
1144                 break;
1145         }
1146 }
1147
1148 void __init r4k_cache_init(void)
1149 {
1150         extern void build_clear_page(void);
1151         extern void build_copy_page(void);
1152         extern char except_vec2_generic;
1153         struct cpuinfo_mips *c = &current_cpu_data;
1154
1155         /* Default cache error handler for R4000 and R5000 family */
1156         set_uncached_handler (0x100, &except_vec2_generic, 0x80);
1157
1158         probe_pcache();
1159         setup_scache();
1160
1161         r4k_blast_dcache_page_setup();
1162         r4k_blast_dcache_page_indexed_setup();
1163         r4k_blast_dcache_setup();
1164         r4k_blast_icache_page_setup();
1165         r4k_blast_icache_page_indexed_setup();
1166         r4k_blast_icache_setup();
1167         r4k_blast_scache_page_setup();
1168         r4k_blast_scache_page_indexed_setup();
1169         r4k_blast_scache_setup();
1170
1171         /*
1172          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1173          * This code supports virtually indexed processors and will be
1174          * unnecessarily inefficient on physically indexed processors.
1175          */
1176         shm_align_mask = max_t( unsigned long,
1177                                 c->dcache.sets * c->dcache.linesz - 1,
1178                                 PAGE_SIZE - 1);
1179
1180         flush_cache_all         = r4k_flush_cache_all;
1181         __flush_cache_all       = r4k___flush_cache_all;
1182         flush_cache_mm          = r4k_flush_cache_mm;
1183         flush_cache_page        = r4k_flush_cache_page;
1184         flush_icache_page       = r4k_flush_icache_page;
1185         flush_cache_range       = r4k_flush_cache_range;
1186
1187         flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
1188         flush_icache_all        = r4k_flush_icache_all;
1189         flush_data_cache_page   = r4k_flush_data_cache_page;
1190         flush_icache_range      = r4k_flush_icache_range;
1191
1192 #ifdef CONFIG_DMA_NONCOHERENT
1193         _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
1194         _dma_cache_wback        = r4k_dma_cache_wback_inv;
1195         _dma_cache_inv          = r4k_dma_cache_inv;
1196 #endif
1197
1198         build_clear_page();
1199         build_copy_page();
1200         local_r4k___flush_cache_all(NULL);
1201         coherency_setup();
1202 }