2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
5 * ########################################################################
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 * ########################################################################
22 * Interrupt exception dispatch code.
25 #include <linux/config.h>
28 #include <asm/mipsregs.h>
29 #include <asm/regdef.h>
30 #include <asm/stackframe.h>
31 #include <asm/mips-boards/maltaint.h>
34 * IRQs on the Malta board look basically (barring software IRQs which we
35 * don't use at all and all external interrupt sources are combined together
36 * on hardware interrupt 0 (MIPS IRQ 2)) like:
40 * 0 Software (ignored)
41 * 1 Software (ignored)
42 * 2 Combined hardware interrupt (hw0)
43 * 3 Hardware (ignored)
44 * 4 Hardware (ignored)
45 * 5 Hardware (ignored)
46 * 6 Hardware (ignored)
47 * 7 R4k timer (what we use)
49 * We handle the IRQ according to _our_ priority which is:
51 * Highest ---- R4k Timer
52 * Lowest ---- Combined hardware interrupt
54 * then we just return, if multiple IRQs are pending then we will just take
55 * another exception, big deal.
62 NESTED(mipsIRQ, PT_SIZE, sp)
67 mfc0 s0, CP0_CAUSE # get irq bits
68 mfc0 s1, CP0_STATUS # get irq mask
69 andi s0, ST0_IM # CAUSE.CE may be non-zero!
72 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
102 li a1, MIPSCPU_INT_I8259A
104 addu a0, MIPSCPU_INT_BASE
106 jal malta_hw0_irqdispatch