2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 * Interrupt exception dispatch code.
20 #include <linux/config.h>
23 #include <asm/mipsregs.h>
24 #include <asm/regdef.h>
25 #include <asm/stackframe.h>
26 #include <asm/mips-boards/atlasint.h>
29 * Furthermore, the IRQs on the MIPS board look basically (barring software
30 * IRQs which we don't use at all and all external interrupt sources are
31 * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
35 * 0 Software (ignored)
36 * 1 Software (ignored)
37 * 2 Combined hardware interrupt (hw0)
38 * 3 Hardware (ignored)
39 * 4 Hardware (ignored)
40 * 5 Hardware (ignored)
41 * 6 Hardware (ignored)
42 * 7 R4k timer (what we use)
44 * Note: On the SEAD board thing are a little bit different.
45 * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
48 * We handle the IRQ according to _our_ priority which is:
50 * Highest ---- R4k Timer
51 * Lowest ---- Combined hardware interrupt
53 * then we just return, if multiple IRQs are pending then we will just take
54 * another exception, big deal.
61 NESTED(mipsIRQ, PT_SIZE, sp)
66 mfc0 s0, CP0_CAUSE # get irq bits
67 mfc0 s1, CP0_STATUS # get irq mask
68 andi s0, ST0_IM # CAUSE.CE may be non-zero!
71 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
101 li a1, MIPSCPU_INT_ATLAS
103 addu a0, MIPSCPU_INT_BASE
105 jal atlas_hw0_irqdispatch