arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004  MIPS Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/stddef.h>
  18
  19 #include <asm/bugs.h>
  20 #include <asm/cpu.h>
  21 #include <asm/fpu.h>
  22 #include <asm/mipsregs.h>
  23 #include <asm/system.h>
  24
  25 /*
  26  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  27  * the implementation of the "wait" feature differs between CPU families. This
  28  * points to the function that implements CPU specific wait.
  29  * The wait instruction stops the pipeline and reduces the power consumption of
  30  * the CPU very much.
  31  */
  32 void (*cpu_wait)(void) = NULL;
  33
  34 static void r3081_wait(void)
  35 {
  36         unsigned long cfg = read_c0_conf();
  37         write_c0_conf(cfg | R30XX_CONF_HALT);
  38 }
  39
  40 static void r39xx_wait(void)
  41 {
  42         local_irq_disable();
  43         if (!need_resched())
  44                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
  45         local_irq_enable();
  46 }
  47
  48 /*
  49  * There is a race when WAIT instruction executed with interrupt
  50  * enabled.
  51  * But it is implementation-dependent wheter the pipelie restarts when
  52  * a non-enabled interrupt is requested.
  53  */
  54 static void r4k_wait(void)
  55 {
  56         __asm__("       .set    mips3                   \n"
  57                 "       wait                            \n"
  58                 "       .set    mips0                   \n");
  59 }
  60
  61 /*
  62  * This variant is preferable as it allows testing need_resched and going to
  63  * sleep depending on the outcome atomically.  Unfortunately the "It is
  64  * implementation-dependent whether the pipeline restarts when a non-enabled
  65  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
  66  * using this version a gamble.
  67  */
  68 static void r4k_wait_irqoff(void)
  69 {
  70         local_irq_disable();
  71         if (!need_resched())
  72                 __asm__("       .set    mips3           \n"
  73                         "       wait                    \n"
  74                         "       .set    mips0           \n");
  75         local_irq_enable();
  76 }
  77
  78 /* The Au1xxx wait is available only if using 32khz counter or
  79  * external timer source, but specifically not CP0 Counter. */
  80 int allow_au1k_wait;
  81
  82 static void au1k_wait(void)
  83 {
  84         /* using the wait instruction makes CP0 counter unusable */
  85         __asm__("       .set    mips3                   \n"
  86                 "       cache   0x14, 0(%0)             \n"
  87                 "       cache   0x14, 32(%0)            \n"
  88                 "       sync                            \n"
  89                 "       nop                             \n"
  90                 "       wait                            \n"
  91                 "       nop                             \n"
  92                 "       nop                             \n"
  93                 "       nop                             \n"
  94                 "       nop                             \n"
  95                 "       .set    mips0                   \n"
  96                 : : "r" (au1k_wait));
  97 }
  98
  99 static int __initdata nowait = 0;
 100
 101 static int __init wait_disable(char *s)
 102 {
 103         nowait = 1;
 104
 105         return 1;
 106 }
 107
 108 __setup("nowait", wait_disable);
 109
 110 static inline void check_wait(void)
 111 {
 112         struct cpuinfo_mips *c = &current_cpu_data;
 113
 114         if (nowait) {
 115                 printk("Wait instruction disabled.\n");
 116                 return;
 117         }
 118
 119         switch (c->cputype) {
 120         case CPU_R3081:
 121         case CPU_R3081E:
 122                 cpu_wait = r3081_wait;
 123                 break;
 124         case CPU_TX3927:
 125                 cpu_wait = r39xx_wait;
 126                 break;
 127         case CPU_R4200:
 128 /*      case CPU_R4300: */
 129         case CPU_R4600:
 130         case CPU_R4640:
 131         case CPU_R4650:
 132         case CPU_R4700:
 133         case CPU_R5000:
 134         case CPU_NEVADA:
 135         case CPU_RM7000:
 136         case CPU_4KC:
 137         case CPU_4KEC:
 138         case CPU_4KSC:
 139         case CPU_5KC:
 140         case CPU_24K:
 141         case CPU_25KF:
 142         case CPU_34K:
 143         case CPU_74K:
 144         case CPU_PR4450:
 145                 cpu_wait = r4k_wait;
 146                 break;
 147         case CPU_TX49XX:
 148                 cpu_wait = r4k_wait_irqoff;
 149                 break;
 150         case CPU_AU1000:
 151         case CPU_AU1100:
 152         case CPU_AU1500:
 153         case CPU_AU1550:
 154         case CPU_AU1200:
 155                 if (allow_au1k_wait)
 156                         cpu_wait = au1k_wait;
 157                 break;
 158         case CPU_20KC:
 159                 /*
 160                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
 161                  * WAIT on Rev2.0 and Rev3.0 has E16.
 162                  * Rev3.1 WAIT is nop, why bother
 163                  */
 164                 if ((c->processor_id & 0xff) <= 0x64)
 165                         break;
 166
 167                 cpu_wait = r4k_wait;
 168                 break;
 169         case CPU_RM9000:
 170                 if ((c->processor_id & 0x00ff) >= 0x40)
 171                         cpu_wait = r4k_wait;
 172                 break;
 173         default:
 174                 break;
 175         }
 176 }
 177
 178 void __init check_bugs32(void)
 179 {
 180         check_wait();
 181 }
 182
 183 /*
 184  * Probe whether cpu has config register by trying to play with
 185  * alternate cache bit and see whether it matters.
 186  * It's used by cpu_probe to distinguish between R3000A and R3081.
 187  */
 188 static inline int cpu_has_confreg(void)
 189 {
 190 #ifdef CONFIG_CPU_R3000
 191         extern unsigned long r3k_cache_size(unsigned long);
 192         unsigned long size1, size2;
 193         unsigned long cfg = read_c0_conf();
 194
 195         size1 = r3k_cache_size(ST0_ISC);
 196         write_c0_conf(cfg ^ R30XX_CONF_AC);
 197         size2 = r3k_cache_size(ST0_ISC);
 198         write_c0_conf(cfg);
 199         return size1 != size2;
 200 #else
 201         return 0;
 202 #endif
 203 }
 204
 205 /*
 206  * Get the FPU Implementation/Revision.
 207  */
 208 static inline unsigned long cpu_get_fpu_id(void)
 209 {
 210         unsigned long tmp, fpu_id;
 211
 212         tmp = read_c0_status();
 213         __enable_fpu();
 214         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 215         write_c0_status(tmp);
 216         return fpu_id;
 217 }
 218
 219 /*
 220  * Check the CPU has an FPU the official way.
 221  */
 222 static inline int __cpu_has_fpu(void)
 223 {
 224         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 225 }
 226
 227 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 228                 | MIPS_CPU_COUNTER)
 229
 230 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
 231 {
 232         switch (c->processor_id & 0xff00) {
 233         case PRID_IMP_R2000:
 234                 c->cputype = CPU_R2000;
 235                 c->isa_level = MIPS_CPU_ISA_I;
 236                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 237                              MIPS_CPU_NOFPUEX;
 238                 if (__cpu_has_fpu())
 239                         c->options |= MIPS_CPU_FPU;
 240                 c->tlbsize = 64;
 241                 break;
 242         case PRID_IMP_R3000:
 243                 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
 244                         if (cpu_has_confreg())
 245                                 c->cputype = CPU_R3081E;
 246                         else
 247                                 c->cputype = CPU_R3000A;
 248                 else
 249                         c->cputype = CPU_R3000;
 250                 c->isa_level = MIPS_CPU_ISA_I;
 251                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 252                              MIPS_CPU_NOFPUEX;
 253                 if (__cpu_has_fpu())
 254                         c->options |= MIPS_CPU_FPU;
 255                 c->tlbsize = 64;
 256                 break;
 257         case PRID_IMP_R4000:
 258                 if (read_c0_config() & CONF_SC) {
 259                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 260                                 c->cputype = CPU_R4400PC;
 261                         else
 262                                 c->cputype = CPU_R4000PC;
 263                 } else {
 264                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 265                                 c->cputype = CPU_R4400SC;
 266                         else
 267                                 c->cputype = CPU_R4000SC;
 268                 }
 269
 270                 c->isa_level = MIPS_CPU_ISA_III;
 271                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 272                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 273                              MIPS_CPU_LLSC;
 274                 c->tlbsize = 48;
 275                 break;
 276         case PRID_IMP_VR41XX:
 277                 switch (c->processor_id & 0xf0) {
 278                 case PRID_REV_VR4111:
 279                         c->cputype = CPU_VR4111;
 280                         break;
 281                 case PRID_REV_VR4121:
 282                         c->cputype = CPU_VR4121;
 283                         break;
 284                 case PRID_REV_VR4122:
 285                         if ((c->processor_id & 0xf) < 0x3)
 286                                 c->cputype = CPU_VR4122;
 287                         else
 288                                 c->cputype = CPU_VR4181A;
 289                         break;
 290                 case PRID_REV_VR4130:
 291                         if ((c->processor_id & 0xf) < 0x4)
 292                                 c->cputype = CPU_VR4131;
 293                         else
 294                                 c->cputype = CPU_VR4133;
 295                         break;
 296                 default:
 297                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 298                         c->cputype = CPU_VR41XX;
 299                         break;
 300                 }
 301                 c->isa_level = MIPS_CPU_ISA_III;
 302                 c->options = R4K_OPTS;
 303                 c->tlbsize = 32;
 304                 break;
 305         case PRID_IMP_R4300:
 306                 c->cputype = CPU_R4300;
 307                 c->isa_level = MIPS_CPU_ISA_III;
 308                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 309                              MIPS_CPU_LLSC;
 310                 c->tlbsize = 32;
 311                 break;
 312         case PRID_IMP_R4600:
 313                 c->cputype = CPU_R4600;
 314                 c->isa_level = MIPS_CPU_ISA_III;
 315                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 316                              MIPS_CPU_LLSC;
 317                 c->tlbsize = 48;
 318                 break;
 319         #if 0
 320         case PRID_IMP_R4650:
 321                 /*
 322                  * This processor doesn't have an MMU, so it's not
 323                  * "real easy" to run Linux on it. It is left purely
 324                  * for documentation.  Commented out because it shares
 325                  * it's c0_prid id number with the TX3900.
 326                  */
 327                 c->cputype = CPU_R4650;
 328                 c->isa_level = MIPS_CPU_ISA_III;
 329                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 330                 c->tlbsize = 48;
 331                 break;
 332         #endif
 333         case PRID_IMP_TX39:
 334                 c->isa_level = MIPS_CPU_ISA_I;
 335                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 336
 337                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 338                         c->cputype = CPU_TX3927;
 339                         c->tlbsize = 64;
 340                 } else {
 341                         switch (c->processor_id & 0xff) {
 342                         case PRID_REV_TX3912:
 343                                 c->cputype = CPU_TX3912;
 344                                 c->tlbsize = 32;
 345                                 break;
 346                         case PRID_REV_TX3922:
 347                                 c->cputype = CPU_TX3922;
 348                                 c->tlbsize = 64;
 349                                 break;
 350                         default:
 351                                 c->cputype = CPU_UNKNOWN;
 352                                 break;
 353                         }
 354                 }
 355                 break;
 356         case PRID_IMP_R4700:
 357                 c->cputype = CPU_R4700;
 358                 c->isa_level = MIPS_CPU_ISA_III;
 359                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 360                              MIPS_CPU_LLSC;
 361                 c->tlbsize = 48;
 362                 break;
 363         case PRID_IMP_TX49:
 364                 c->cputype = CPU_TX49XX;
 365                 c->isa_level = MIPS_CPU_ISA_III;
 366                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 367                 if (!(c->processor_id & 0x08))
 368                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 369                 c->tlbsize = 48;
 370                 break;
 371         case PRID_IMP_R5000:
 372                 c->cputype = CPU_R5000;
 373                 c->isa_level = MIPS_CPU_ISA_IV;
 374                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 375                              MIPS_CPU_LLSC;
 376                 c->tlbsize = 48;
 377                 break;
 378         case PRID_IMP_R5432:
 379                 c->cputype = CPU_R5432;
 380                 c->isa_level = MIPS_CPU_ISA_IV;
 381                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 382                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 383                 c->tlbsize = 48;
 384                 break;
 385         case PRID_IMP_R5500:
 386                 c->cputype = CPU_R5500;
 387                 c->isa_level = MIPS_CPU_ISA_IV;
 388                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 389                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 390                 c->tlbsize = 48;
 391                 break;
 392         case PRID_IMP_NEVADA:
 393                 c->cputype = CPU_NEVADA;
 394                 c->isa_level = MIPS_CPU_ISA_IV;
 395                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 396                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 397                 c->tlbsize = 48;
 398                 break;
 399         case PRID_IMP_R6000:
 400                 c->cputype = CPU_R6000;
 401                 c->isa_level = MIPS_CPU_ISA_II;
 402                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 403                              MIPS_CPU_LLSC;
 404                 c->tlbsize = 32;
 405                 break;
 406         case PRID_IMP_R6000A:
 407                 c->cputype = CPU_R6000A;
 408                 c->isa_level = MIPS_CPU_ISA_II;
 409                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 410                              MIPS_CPU_LLSC;
 411                 c->tlbsize = 32;
 412                 break;
 413         case PRID_IMP_RM7000:
 414                 c->cputype = CPU_RM7000;
 415                 c->isa_level = MIPS_CPU_ISA_IV;
 416                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 417                              MIPS_CPU_LLSC;
 418                 /*
 419                  * Undocumented RM7000:  Bit 29 in the info register of
 420                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 421                  * entries.
 422                  *
 423                  * 29      1 =>    64 entry JTLB
 424                  *         0 =>    48 entry JTLB
 425                  */
 426                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 427                 break;
 428         case PRID_IMP_RM9000:
 429                 c->cputype = CPU_RM9000;
 430                 c->isa_level = MIPS_CPU_ISA_IV;
 431                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 432                              MIPS_CPU_LLSC;
 433                 /*
 434                  * Bit 29 in the info register of the RM9000
 435                  * indicates if the TLB has 48 or 64 entries.
 436                  *
 437                  * 29      1 =>    64 entry JTLB
 438                  *         0 =>    48 entry JTLB
 439                  */
 440                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 441                 break;
 442         case PRID_IMP_R8000:
 443                 c->cputype = CPU_R8000;
 444                 c->isa_level = MIPS_CPU_ISA_IV;
 445                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 446                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 447                              MIPS_CPU_LLSC;
 448                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 449                 break;
 450         case PRID_IMP_R10000:
 451                 c->cputype = CPU_R10000;
 452                 c->isa_level = MIPS_CPU_ISA_IV;
 453                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 454                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 455                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 456                              MIPS_CPU_LLSC;
 457                 c->tlbsize = 64;
 458                 break;
 459         case PRID_IMP_R12000:
 460                 c->cputype = CPU_R12000;
 461                 c->isa_level = MIPS_CPU_ISA_IV;
 462                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 463                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 464                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 465                              MIPS_CPU_LLSC;
 466                 c->tlbsize = 64;
 467                 break;
 468         case PRID_IMP_R14000:
 469                 c->cputype = CPU_R14000;
 470                 c->isa_level = MIPS_CPU_ISA_IV;
 471                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 472                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 473                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 474                              MIPS_CPU_LLSC;
 475                 c->tlbsize = 64;
 476                 break;
 477         }
 478 }
 479
 480 static char unknown_isa[] __initdata = KERN_ERR \
 481         "Unsupported ISA type, c0.config0: %d.";
 482
 483 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 484 {
 485         unsigned int config0;
 486         int isa;
 487
 488         config0 = read_c0_config();
 489
 490         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 491                 c->options |= MIPS_CPU_TLB;
 492         isa = (config0 & MIPS_CONF_AT) >> 13;
 493         switch (isa) {
 494         case 0:
 495                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 496                 case 0:
 497                         c->isa_level = MIPS_CPU_ISA_M32R1;
 498                         break;
 499                 case 1:
 500                         c->isa_level = MIPS_CPU_ISA_M32R2;
 501                         break;
 502                 default:
 503                         goto unknown;
 504                 }
 505                 break;
 506         case 2:
 507                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 508                 case 0:
 509                         c->isa_level = MIPS_CPU_ISA_M64R1;
 510                         break;
 511                 case 1:
 512                         c->isa_level = MIPS_CPU_ISA_M64R2;
 513                         break;
 514                 default:
 515                         goto unknown;
 516                 }
 517                 break;
 518         default:
 519                 goto unknown;
 520         }
 521
 522         return config0 & MIPS_CONF_M;
 523
 524 unknown:
 525         panic(unknown_isa, config0);
 526 }
 527
 528 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 529 {
 530         unsigned int config1;
 531
 532         config1 = read_c0_config1();
 533
 534         if (config1 & MIPS_CONF1_MD)
 535                 c->ases |= MIPS_ASE_MDMX;
 536         if (config1 & MIPS_CONF1_WR)
 537                 c->options |= MIPS_CPU_WATCH;
 538         if (config1 & MIPS_CONF1_CA)
 539                 c->ases |= MIPS_ASE_MIPS16;
 540         if (config1 & MIPS_CONF1_EP)
 541                 c->options |= MIPS_CPU_EJTAG;
 542         if (config1 & MIPS_CONF1_FP) {
 543                 c->options |= MIPS_CPU_FPU;
 544                 c->options |= MIPS_CPU_32FPR;
 545         }
 546         if (cpu_has_tlb)
 547                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 548
 549         return config1 & MIPS_CONF_M;
 550 }
 551
 552 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 553 {
 554         unsigned int config2;
 555
 556         config2 = read_c0_config2();
 557
 558         if (config2 & MIPS_CONF2_SL)
 559                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 560
 561         return config2 & MIPS_CONF_M;
 562 }
 563
 564 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 565 {
 566         unsigned int config3;
 567
 568         config3 = read_c0_config3();
 569
 570         if (config3 & MIPS_CONF3_SM)
 571                 c->ases |= MIPS_ASE_SMARTMIPS;
 572         if (config3 & MIPS_CONF3_DSP)
 573                 c->ases |= MIPS_ASE_DSP;
 574         if (config3 & MIPS_CONF3_VINT)
 575                 c->options |= MIPS_CPU_VINT;
 576         if (config3 & MIPS_CONF3_VEIC)
 577                 c->options |= MIPS_CPU_VEIC;
 578         if (config3 & MIPS_CONF3_MT)
 579                 c->ases |= MIPS_ASE_MIPSMT;
 580
 581         return config3 & MIPS_CONF_M;
 582 }
 583
 584 static void __init decode_configs(struct cpuinfo_mips *c)
 585 {
 586         /* MIPS32 or MIPS64 compliant CPU.  */
 587         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 588                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 589
 590         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 591
 592         /* Read Config registers.  */
 593         if (!decode_config0(c))
 594                 return;                 /* actually worth a panic() */
 595         if (!decode_config1(c))
 596                 return;
 597         if (!decode_config2(c))
 598                 return;
 599         if (!decode_config3(c))
 600                 return;
 601 }
 602
 603 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
 604 {
 605         decode_configs(c);
 606         switch (c->processor_id & 0xff00) {
 607         case PRID_IMP_4KC:
 608                 c->cputype = CPU_4KC;
 609                 break;
 610         case PRID_IMP_4KEC:
 611                 c->cputype = CPU_4KEC;
 612                 break;
 613         case PRID_IMP_4KECR2:
 614                 c->cputype = CPU_4KEC;
 615                 break;
 616         case PRID_IMP_4KSC:
 617         case PRID_IMP_4KSD:
 618                 c->cputype = CPU_4KSC;
 619                 break;
 620         case PRID_IMP_5KC:
 621                 c->cputype = CPU_5KC;
 622                 break;
 623         case PRID_IMP_20KC:
 624                 c->cputype = CPU_20KC;
 625                 break;
 626         case PRID_IMP_24K:
 627         case PRID_IMP_24KE:
 628                 c->cputype = CPU_24K;
 629                 break;
 630         case PRID_IMP_25KF:
 631                 c->cputype = CPU_25KF;
 632                 break;
 633         case PRID_IMP_34K:
 634                 c->cputype = CPU_34K;
 635                 break;
 636         case PRID_IMP_74K:
 637                 c->cputype = CPU_74K;
 638                 break;
 639         }
 640 }
 641
 642 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
 643 {
 644         decode_configs(c);
 645         switch (c->processor_id & 0xff00) {
 646         case PRID_IMP_AU1_REV1:
 647         case PRID_IMP_AU1_REV2:
 648                 switch ((c->processor_id >> 24) & 0xff) {
 649                 case 0:
 650                         c->cputype = CPU_AU1000;
 651                         break;
 652                 case 1:
 653                         c->cputype = CPU_AU1500;
 654                         break;
 655                 case 2:
 656                         c->cputype = CPU_AU1100;
 657                         break;
 658                 case 3:
 659                         c->cputype = CPU_AU1550;
 660                         break;
 661                 case 4:
 662                         c->cputype = CPU_AU1200;
 663                         break;
 664                 default:
 665                         panic("Unknown Au Core!");
 666                         break;
 667                 }
 668                 break;
 669         }
 670 }
 671
 672 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
 673 {
 674         decode_configs(c);
 675
 676         /*
 677          * For historical reasons the SB1 comes with it's own variant of
 678          * cache code which eventually will be folded into c-r4k.c.  Until
 679          * then we pretend it's got it's own cache architecture.
 680          */
 681         c->options &= ~MIPS_CPU_4K_CACHE;
 682         c->options |= MIPS_CPU_SB1_CACHE;
 683
 684         switch (c->processor_id & 0xff00) {
 685         case PRID_IMP_SB1:
 686                 c->cputype = CPU_SB1;
 687                 /* FPU in pass1 is known to have issues. */
 688                 if ((c->processor_id & 0xff) < 0x02)
 689                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 690                 break;
 691         case PRID_IMP_SB1A:
 692                 c->cputype = CPU_SB1A;
 693                 break;
 694         }
 695 }
 696
 697 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
 698 {
 699         decode_configs(c);
 700         switch (c->processor_id & 0xff00) {
 701         case PRID_IMP_SR71000:
 702                 c->cputype = CPU_SR71000;
 703                 c->scache.ways = 8;
 704                 c->tlbsize = 64;
 705                 break;
 706         }
 707 }
 708
 709 static inline void cpu_probe_philips(struct cpuinfo_mips *c)
 710 {
 711         decode_configs(c);
 712         switch (c->processor_id & 0xff00) {
 713         case PRID_IMP_PR4450:
 714                 c->cputype = CPU_PR4450;
 715                 c->isa_level = MIPS_CPU_ISA_M32R1;
 716                 break;
 717         default:
 718                 panic("Unknown Philips Core!"); /* REVISIT: die? */
 719                 break;
 720         }
 721 }
 722
 723
 724 __init void cpu_probe(void)
 725 {
 726         struct cpuinfo_mips *c = &current_cpu_data;
 727
 728         c->processor_id = PRID_IMP_UNKNOWN;
 729         c->fpu_id       = FPIR_IMP_NONE;
 730         c->cputype      = CPU_UNKNOWN;
 731
 732         c->processor_id = read_c0_prid();
 733         switch (c->processor_id & 0xff0000) {
 734         case PRID_COMP_LEGACY:
 735                 cpu_probe_legacy(c);
 736                 break;
 737         case PRID_COMP_MIPS:
 738                 cpu_probe_mips(c);
 739                 break;
 740         case PRID_COMP_ALCHEMY:
 741                 cpu_probe_alchemy(c);
 742                 break;
 743         case PRID_COMP_SIBYTE:
 744                 cpu_probe_sibyte(c);
 745                 break;
 746         case PRID_COMP_SANDCRAFT:
 747                 cpu_probe_sandcraft(c);
 748                 break;
 749         case PRID_COMP_PHILIPS:
 750                 cpu_probe_philips(c);
 751                 break;
 752         default:
 753                 c->cputype = CPU_UNKNOWN;
 754         }
 755         if (c->options & MIPS_CPU_FPU) {
 756                 c->fpu_id = cpu_get_fpu_id();
 757
 758                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
 759                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
 760                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
 761                     c->isa_level == MIPS_CPU_ISA_M64R2) {
 762                         if (c->fpu_id & MIPS_FPIR_3D)
 763                                 c->ases |= MIPS_ASE_MIPS3D;
 764                 }
 765         }
 766 }
 767
 768 __init void cpu_report(void)
 769 {
 770         struct cpuinfo_mips *c = &current_cpu_data;
 771
 772         printk("CPU revision is: %08x\n", c->processor_id);
 773         if (c->options & MIPS_CPU_FPU)
 774                 printk("FPU revision is: %08x\n", c->fpu_id);
 775 }