2 * arch/mips/emma2rh/markeins/irq_markeins.c
3 * This file defines the irq handler for Mark-eins.
5 * Copyright (C) NEC Electronics Corporation 2004-2006
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
9 * Copyright 2001 MontaVista Software Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/interrupt.h>
26 #include <linux/irq.h>
27 #include <linux/types.h>
28 #include <linux/ptrace.h>
30 #include <asm/debug.h>
31 #include <asm/emma2rh/emma2rh.h>
33 static int emma2rh_sw_irq_base = -1;
34 static int emma2rh_gpio_irq_base = -1;
36 void ll_emma2rh_sw_irq_enable(int reg);
37 void ll_emma2rh_sw_irq_disable(int reg);
38 void ll_emma2rh_gpio_irq_enable(int reg);
39 void ll_emma2rh_gpio_irq_disable(int reg);
41 static void emma2rh_sw_irq_enable(unsigned int irq)
43 ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base);
46 static void emma2rh_sw_irq_disable(unsigned int irq)
48 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
51 static void emma2rh_sw_irq_end(unsigned int irq)
53 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
54 ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base);
57 struct irq_chip emma2rh_sw_irq_controller = {
58 .typename = "emma2rh_sw_irq",
59 .ack = emma2rh_sw_irq_disable,
60 .mask = emma2rh_sw_irq_disable,
61 .mask_ack = emma2rh_sw_irq_disable,
62 .unmask = emma2rh_sw_irq_enable,
63 .end = emma2rh_sw_irq_end,
66 void emma2rh_sw_irq_init(u32 irq_base)
70 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++)
71 set_irq_chip_and_handler(i, &emma2rh_sw_irq_controller,
74 emma2rh_sw_irq_base = irq_base;
77 void ll_emma2rh_sw_irq_enable(int irq)
82 db_assert(irq < NUM_EMMA2RH_IRQ_SW);
84 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
86 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
89 void ll_emma2rh_sw_irq_disable(int irq)
96 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
98 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
101 static void emma2rh_gpio_irq_enable(unsigned int irq)
103 ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base);
106 static void emma2rh_gpio_irq_disable(unsigned int irq)
108 ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base);
111 static void emma2rh_gpio_irq_ack(unsigned int irq)
113 irq -= emma2rh_gpio_irq_base;
114 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
115 ll_emma2rh_gpio_irq_disable(irq);
118 static void emma2rh_gpio_irq_end(unsigned int irq)
120 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
121 ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base);
124 struct irq_chip emma2rh_gpio_irq_controller = {
125 .typename = "emma2rh_gpio_irq",
126 .ack = emma2rh_gpio_irq_ack,
127 .mask = emma2rh_gpio_irq_disable,
128 .mask_ack = emma2rh_gpio_irq_ack,
129 .unmask = emma2rh_gpio_irq_enable,
130 .end = emma2rh_gpio_irq_end,
133 void emma2rh_gpio_irq_init(u32 irq_base)
137 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++)
138 set_irq_chip(i, &emma2rh_gpio_irq_controller);
140 emma2rh_gpio_irq_base = irq_base;
143 void ll_emma2rh_gpio_irq_enable(int irq)
148 db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
150 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
152 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
155 void ll_emma2rh_gpio_irq_disable(int irq)
160 db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
162 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
164 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);