2 * arch/mips/emma2rh/markeins/irq_markeins.c
3 * This file defines the irq handler for Mark-eins.
5 * Copyright (C) NEC Electronics Corporation 2004-2006
7 * This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
9 * Copyright 2001 MontaVista Software Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/interrupt.h>
26 #include <linux/irq.h>
27 #include <linux/types.h>
28 #include <linux/ptrace.h>
30 #include <asm/debug.h>
31 #include <asm/emma/emma2rh.h>
33 void ll_emma2rh_sw_irq_enable(int reg);
34 void ll_emma2rh_sw_irq_disable(int reg);
35 void ll_emma2rh_gpio_irq_enable(int reg);
36 void ll_emma2rh_gpio_irq_disable(int reg);
38 static void emma2rh_sw_irq_enable(unsigned int irq)
40 ll_emma2rh_sw_irq_enable(irq - EMMA2RH_SW_IRQ_BASE);
43 static void emma2rh_sw_irq_disable(unsigned int irq)
45 ll_emma2rh_sw_irq_disable(irq - EMMA2RH_SW_IRQ_BASE);
48 struct irq_chip emma2rh_sw_irq_controller = {
49 .name = "emma2rh_sw_irq",
50 .ack = emma2rh_sw_irq_disable,
51 .mask = emma2rh_sw_irq_disable,
52 .mask_ack = emma2rh_sw_irq_disable,
53 .unmask = emma2rh_sw_irq_enable,
56 void emma2rh_sw_irq_init(void)
60 for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
61 set_irq_chip_and_handler(EMMA2RH_SW_IRQ_BASE + i,
62 &emma2rh_sw_irq_controller,
66 void ll_emma2rh_sw_irq_enable(int irq)
71 db_assert(irq < NUM_EMMA2RH_IRQ_SW);
73 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
75 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
78 void ll_emma2rh_sw_irq_disable(int irq)
85 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
87 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
90 static void emma2rh_gpio_irq_enable(unsigned int irq)
92 ll_emma2rh_gpio_irq_enable(irq - EMMA2RH_GPIO_IRQ_BASE);
95 static void emma2rh_gpio_irq_disable(unsigned int irq)
97 ll_emma2rh_gpio_irq_disable(irq - EMMA2RH_GPIO_IRQ_BASE);
100 static void emma2rh_gpio_irq_ack(unsigned int irq)
102 irq -= EMMA2RH_GPIO_IRQ_BASE;
103 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
104 ll_emma2rh_gpio_irq_disable(irq);
107 static void emma2rh_gpio_irq_end(unsigned int irq)
109 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
110 ll_emma2rh_gpio_irq_enable(irq - EMMA2RH_GPIO_IRQ_BASE);
113 struct irq_chip emma2rh_gpio_irq_controller = {
114 .name = "emma2rh_gpio_irq",
115 .ack = emma2rh_gpio_irq_ack,
116 .mask = emma2rh_gpio_irq_disable,
117 .mask_ack = emma2rh_gpio_irq_ack,
118 .unmask = emma2rh_gpio_irq_enable,
119 .end = emma2rh_gpio_irq_end,
122 void emma2rh_gpio_irq_init(void)
126 for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
127 set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i,
128 &emma2rh_gpio_irq_controller);
131 void ll_emma2rh_gpio_irq_enable(int irq)
136 db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
138 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
140 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
143 void ll_emma2rh_gpio_irq_disable(int irq)
148 db_assert(irq < NUM_EMMA2RH_IRQ_GPIO);
150 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
152 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);