arch/mips/au1000/pb1200/irqmap.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  *      Au1xxx irq map table
   4  *
   5  *  This program is free software; you can redistribute  it and/or modify it
   6  *  under  the terms of  the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the  License, or (at your
   8  *  option) any later version.
   9  *
  10  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  11  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  13  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  14  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  15  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  16  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  17  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  18  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  19  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  20  *
  21  *  You should have received a copy of the  GNU General Public License along
  22  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  23  *  675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28
  29 #include <asm/mach-au1x00/au1000.h>
  30
  31 #ifdef CONFIG_MIPS_PB1200
  32 #include <asm/mach-pb1x00/pb1200.h>
  33 #endif
  34
  35 #ifdef CONFIG_MIPS_DB1200
  36 #include <asm/mach-db1x00/db1200.h>
  37 #define PB1200_INT_BEGIN DB1200_INT_BEGIN
  38 #define PB1200_INT_END DB1200_INT_END
  39 #endif
  40
  41 struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
  42         { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade
  43 };
  44
  45 int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
  46
  47 /*
  48  *      Support for External interrupts on the PbAu1200 Development platform.
  49  */
  50 static volatile int pb1200_cascade_en=0;
  51
  52 irqreturn_t pb1200_cascade_handler( int irq, void *dev_id)
  53 {
  54         unsigned short bisr = bcsr->int_status;
  55         int extirq_nr = 0;
  56
  57         /* Clear all the edge interrupts. This has no effect on level */
  58         bcsr->int_status = bisr;
  59         for( ; bisr; bisr &= (bisr-1) )
  60         {
  61                 extirq_nr = PB1200_INT_BEGIN + __ffs(bisr);
  62                 /* Ack and dispatch IRQ */
  63                 do_IRQ(extirq_nr);
  64         }
  65
  66         return IRQ_RETVAL(1);
  67 }
  68
  69 inline void pb1200_enable_irq(unsigned int irq_nr)
  70 {
  71         bcsr->intset_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
  72         bcsr->intset = 1<<(irq_nr - PB1200_INT_BEGIN);
  73 }
  74
  75 inline void pb1200_disable_irq(unsigned int irq_nr)
  76 {
  77         bcsr->intclr_mask = 1<<(irq_nr - PB1200_INT_BEGIN);
  78         bcsr->intclr = 1<<(irq_nr - PB1200_INT_BEGIN);
  79 }
  80
  81 static unsigned int pb1200_setup_cascade(void)
  82 {
  83         int err;
  84
  85         err = request_irq(AU1000_GPIO_7, &pb1200_cascade_handler,
  86                           0, "Pb1200 Cascade", &pb1200_cascade_handler);
  87         if (err)
  88                 return err;
  89
  90         return 0;
  91 }
  92
  93 static unsigned int pb1200_startup_irq(unsigned int irq)
  94 {
  95         if (++pb1200_cascade_en == 1) {
  96                 int res;
  97
  98                 res = pb1200_setup_cascade();
  99                 if (res)
 100                         return res;
 101         }
 102
 103         pb1200_enable_irq(irq);
 104
 105         return 0;
 106 }
 107
 108 static void pb1200_shutdown_irq(unsigned int irq)
 109 {
 110         pb1200_disable_irq(irq);
 111         if (--pb1200_cascade_en == 0)
 112                 free_irq(AU1000_GPIO_7, &pb1200_cascade_handler);
 113 }
 114
 115 static struct irq_chip external_irq_type = {
 116 #ifdef CONFIG_MIPS_PB1200
 117         .name = "Pb1200 Ext",
 118 #endif
 119 #ifdef CONFIG_MIPS_DB1200
 120         .name = "Db1200 Ext",
 121 #endif
 122         .startup  = pb1200_startup_irq,
 123         .shutdown = pb1200_shutdown_irq,
 124         .ack      = pb1200_disable_irq,
 125         .mask     = pb1200_disable_irq,
 126         .mask_ack = pb1200_disable_irq,
 127         .unmask   = pb1200_enable_irq,
 128 };
 129
 130 void _board_init_irq(void)
 131 {
 132         unsigned int irq;
 133
 134 #ifdef CONFIG_MIPS_PB1200
 135         /* We have a problem with CPLD rev3. Enable a workaround */
 136         if (((bcsr->whoami & BCSR_WHOAMI_CPLD) >> 4) <= 3) {
 137                 printk("\nWARNING!!!\n");
 138                 printk("\nWARNING!!!\n");
 139                 printk("\nWARNING!!!\n");
 140                 printk("\nWARNING!!!\n");
 141                 printk("\nWARNING!!!\n");
 142                 printk("\nWARNING!!!\n");
 143                 printk("Pb1200 must be at CPLD rev4. Please have Pb1200\n");
 144                 printk("updated to latest revision. This software will not\n");
 145                 printk("work on anything less than CPLD rev4\n");
 146                 printk("\nWARNING!!!\n");
 147                 printk("\nWARNING!!!\n");
 148                 printk("\nWARNING!!!\n");
 149                 printk("\nWARNING!!!\n");
 150                 printk("\nWARNING!!!\n");
 151                 printk("\nWARNING!!!\n");
 152                 panic("Game over.  Your score is 0.");
 153         }
 154 #endif
 155
 156         for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++) {
 157                 set_irq_chip_and_handler(irq, &external_irq_type,
 158                                          handle_level_irq);
 159                 pb1200_disable_irq(irq);
 160         }
 161
 162         /*
 163          * GPIO_7 can not be hooked here, so it is hooked upon first
 164          * request of any source attached to the cascade
 165          */
 166 }