1 /***************************************************************************/
4 * linux/arch/m68knommu/platform/528x/config.c
6 * Sub-architcture dependant initialization code for the Motorola
9 * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
10 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
13 /***************************************************************************/
15 #include <linux/kernel.h>
16 #include <linux/param.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/platform_device.h>
20 #include <linux/spi/spi.h>
21 #include <linux/spi/flash.h>
23 #include <asm/machdep.h>
24 #include <asm/coldfire.h>
25 #include <asm/mcfsim.h>
26 #include <asm/mcfuart.h>
27 #include <asm/mcfqspi.h>
29 #ifdef CONFIG_MTD_PARTITIONS
30 #include <linux/mtd/partitions.h>
33 /***************************************************************************/
35 void coldfire_reset(void);
36 static void coldfire_qspi_cs_control(u8 cs, u8 command);
38 /***************************************************************************/
40 #if defined(CONFIG_SPI)
42 #if defined(CONFIG_WILDFIRE)
43 #define SPI_NUM_CHIPSELECTS 0x02
44 #define SPI_PAR_VAL 0x07 /* Enable DIN, DOUT, CLK */
45 #define SPI_CS_MASK 0x18
47 #define FLASH_BLOCKSIZE (1024*64)
48 #define FLASH_NUMBLOCKS 16
49 #define FLASH_TYPE "m25p80"
54 #ifdef CONFIG_MTD_PARTITIONS
55 static struct mtd_partition stm25p_partitions[] = {
60 .size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS,
67 #elif defined(CONFIG_WILDFIREMOD)
69 #define SPI_NUM_CHIPSELECTS 0x08
70 #define SPI_PAR_VAL 0x07 /* Enable DIN, DOUT, CLK */
71 #define SPI_CS_MASK 0x78
73 #define FLASH_BLOCKSIZE (1024*64)
74 #define FLASH_NUMBLOCKS 64
75 #define FLASH_TYPE "m25p32"
76 /* Reserve 1M for the kernel parition */
77 #define FLASH_KERNEL_SIZE (1024 * 1024)
82 #ifdef CONFIG_MTD_PARTITIONS
83 static struct mtd_partition stm25p_partitions[] = {
87 .offset = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS - FLASH_KERNEL_SIZE,
88 .size = FLASH_KERNEL_SIZE,
94 .size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS - FLASH_KERNEL_SIZE,
100 .size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS,
107 #define SPI_NUM_CHIPSELECTS 0x04
108 #define SPI_PAR_VAL 0x7F /* Enable DIN, DOUT, CLK, CS0 - CS4 */
112 static struct coldfire_spi_chip flash_chip_info = {
116 .del_after_trans = 1,
120 static struct coldfire_spi_chip mmc_chip_info = {
124 .del_after_trans = 1,
125 .void_write_data = 0xFFFF
130 static struct flash_platform_data stm25p80_platform_data = {
131 .name = "ST M25P80 SPI Flash chip",
132 #ifdef CONFIG_MTD_PARTITIONS
133 .parts = stm25p_partitions,
134 .nr_parts = sizeof(stm25p_partitions) / sizeof(*stm25p_partitions),
140 static struct spi_board_info spi_board_info[] __initdata = {
143 .modalias = "m25p80",
144 .max_speed_hz = 16000000,
146 .chip_select = M25P80_CS,
147 .platform_data = &stm25p80_platform_data,
148 .controller_data = &flash_chip_info
153 .modalias = "mmc_spi",
154 .max_speed_hz = 16000000,
156 .chip_select = MMC_CS,
157 .controller_data = &mmc_chip_info
162 static struct coldfire_spi_master coldfire_master_info = {
164 .num_chipselect = SPI_NUM_CHIPSELECTS,
165 .irq_source = MCF5282_QSPI_IRQ_SOURCE,
166 .irq_vector = MCF5282_QSPI_IRQ_VECTOR,
167 .irq_mask = ((0x01 << MCF5282_QSPI_IRQ_SOURCE) | 0x01),
168 .irq_lp = 0x2B, /* Level 5 and Priority 3 */
169 .par_val = SPI_PAR_VAL,
170 .cs_control = coldfire_qspi_cs_control,
173 static struct resource coldfire_spi_resources[] = {
176 .start = MCF5282_QSPI_PAR,
177 .end = MCF5282_QSPI_PAR,
178 .flags = IORESOURCE_MEM
182 .name = "qspi-module",
183 .start = MCF5282_QSPI_QMR,
184 .end = MCF5282_QSPI_QMR + 0x18,
185 .flags = IORESOURCE_MEM
189 .name = "qspi-int-level",
190 .start = MCF5282_INTC0 + MCFINTC_ICR0 + MCF5282_QSPI_IRQ_SOURCE,
191 .end = MCF5282_INTC0 + MCFINTC_ICR0 + MCF5282_QSPI_IRQ_SOURCE,
192 .flags = IORESOURCE_MEM
196 .name = "qspi-int-mask",
197 .start = MCF5282_INTC0 + MCFINTC_IMRL,
198 .end = MCF5282_INTC0 + MCFINTC_IMRL,
199 .flags = IORESOURCE_MEM
203 static struct platform_device coldfire_spi = {
204 .name = "spi_coldfire",
206 .resource = coldfire_spi_resources,
207 .num_resources = ARRAY_SIZE(coldfire_spi_resources),
209 .platform_data = &coldfire_master_info,
213 static void coldfire_qspi_cs_control(u8 cs, u8 command)
215 u8 cs_bit = ((0x01 << cs) << 3) & SPI_CS_MASK;
217 #if defined(CONFIG_WILDFIRE)
218 u8 cs_mask = ~(((0x01 << cs) << 3) & SPI_CS_MASK);
220 #if defined(CONFIG_WILDFIREMOD)
221 u8 cs_mask = (cs << 3) & SPI_CS_MASK;
225 * Don't do anything if the chip select is not
226 * one of the port qs pins.
228 if (command & QSPI_CS_INIT) {
229 #if defined(CONFIG_WILDFIRE)
230 MCF5282_GPIO_DDRQS |= cs_bit;
231 MCF5282_GPIO_PQSPAR &= ~cs_bit;
234 #if defined(CONFIG_WILDFIREMOD)
235 MCF5282_GPIO_DDRQS |= SPI_CS_MASK;
236 MCF5282_GPIO_PQSPAR &= ~SPI_CS_MASK;
240 if (command & QSPI_CS_ASSERT) {
241 MCF5282_GPIO_PORTQS &= ~SPI_CS_MASK;
242 MCF5282_GPIO_PORTQS |= cs_mask;
243 } else if (command & QSPI_CS_DROP) {
244 MCF5282_GPIO_PORTQS |= SPI_CS_MASK;
248 static int __init spi_dev_init(void)
252 retval = platform_device_register(&coldfire_spi);
256 if (ARRAY_SIZE(spi_board_info))
257 retval = spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
262 #endif /* CONFIG_SPI */
264 /***************************************************************************/
266 static struct mcf_platform_uart m528x_uart_platform[] = {
268 .mapbase = MCF_MBAR + MCFUART_BASE1,
269 .irq = MCFINT_VECBASE + MCFINT_UART0,
272 .mapbase = MCF_MBAR + MCFUART_BASE2,
273 .irq = MCFINT_VECBASE + MCFINT_UART0 + 1,
276 .mapbase = MCF_MBAR + MCFUART_BASE3,
277 .irq = MCFINT_VECBASE + MCFINT_UART0 + 2,
282 static struct platform_device m528x_uart = {
285 .dev.platform_data = m528x_uart_platform,
288 static struct resource m528x_fec_resources[] = {
290 .start = MCF_MBAR + 0x1000,
291 .end = MCF_MBAR + 0x1000 + 0x7ff,
292 .flags = IORESOURCE_MEM,
297 .flags = IORESOURCE_IRQ,
302 .flags = IORESOURCE_IRQ,
307 .flags = IORESOURCE_IRQ,
311 static struct platform_device m528x_fec = {
314 .num_resources = ARRAY_SIZE(m528x_fec_resources),
315 .resource = m528x_fec_resources,
319 static struct platform_device *m528x_devices[] __initdata = {
324 /***************************************************************************/
326 #define INTC0 (MCF_MBAR + MCFICM_INTC0)
328 static void __init m528x_uart_init_line(int line, int irq)
333 if ((line < 0) || (line > 2))
336 /* level 6, line based priority */
337 writeb(0x30+line, INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + line);
339 imr = readl(INTC0 + MCFINTC_IMRL);
340 imr &= ~((1 << (irq - MCFINT_VECBASE)) | 1);
341 writel(imr, INTC0 + MCFINTC_IMRL);
343 /* make sure PUAPAR is set for UART0 and UART1 */
345 port = readb(MCF_MBAR + MCF5282_GPIO_PUAPAR);
346 port |= (0x03 << (line * 2));
347 writeb(port, MCF_MBAR + MCF5282_GPIO_PUAPAR);
351 static void __init m528x_uarts_init(void)
353 const int nrlines = ARRAY_SIZE(m528x_uart_platform);
356 for (line = 0; (line < nrlines); line++)
357 m528x_uart_init_line(line, m528x_uart_platform[line].irq);
360 /***************************************************************************/
362 static void __init m528x_fec_init(void)
367 /* Unmask FEC interrupts at ColdFire interrupt controller */
368 writeb(0x28, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 23);
369 writeb(0x27, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 27);
370 writeb(0x26, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 29);
372 imr = readl(MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
374 writel(imr, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
375 imr = readl(MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
377 writel(imr, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
379 /* Set multi-function pins to ethernet mode for fec0 */
380 v16 = readw(MCF_IPSBAR + 0x100056);
381 writew(v16 | 0xf00, MCF_IPSBAR + 0x100056);
382 writeb(0xc0, MCF_IPSBAR + 0x100058);
385 /***************************************************************************/
387 void mcf_disableall(void)
389 *((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH)) = 0xffffffff;
390 *((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL)) = 0xffffffff;
393 /***************************************************************************/
395 void mcf_autovector(unsigned int vec)
397 /* Everything is auto-vectored on the 5272 */
400 /***************************************************************************/
402 #ifdef CONFIG_WILDFIRE
403 void wildfire_halt(void)
405 writeb(0, 0x30000007);
406 writeb(0x2, 0x30000007);
410 #ifdef CONFIG_WILDFIREMOD
411 void wildfiremod_halt(void)
413 printk(KERN_INFO "WildFireMod hibernating...\n");
415 /* Set portE.5 to Digital IO */
416 MCF5282_GPIO_PEPAR &= ~(1 << (5 * 2));
418 /* Make portE.5 an output */
419 MCF5282_GPIO_DDRE |= (1 << 5);
421 /* Now toggle portE.5 from low to high */
422 MCF5282_GPIO_PORTE &= ~(1 << 5);
423 MCF5282_GPIO_PORTE |= (1 << 5);
425 printk(KERN_EMERG "Failed to hibernate. Halting!\n");
429 void __init config_BSP(char *commandp, int size)
433 #ifdef CONFIG_WILDFIRE
434 mach_halt = wildfire_halt;
436 #ifdef CONFIG_WILDFIREMOD
437 mach_halt = wildfiremod_halt;
441 /***************************************************************************/
443 static int __init init_BSP(void)
447 platform_add_devices(m528x_devices, ARRAY_SIZE(m528x_devices));
451 arch_initcall(init_BSP);
453 /***************************************************************************/