arch/m68k/q40/config.c

   1 /*
   2  *  arch/m68k/q40/config.c
   3  *
   4  *  Copyright (C) 1999 Richard Zidlicky
   5  *
   6  * originally based on:
   7  *
   8  *  linux/bvme/config.c
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file README.legal in the main directory of this archive
  12  * for more details.
  13  */
  14
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/mm.h>
  18 #include <linux/tty.h>
  19 #include <linux/console.h>
  20 #include <linux/linkage.h>
  21 #include <linux/init.h>
  22 #include <linux/major.h>
  23 #include <linux/serial_reg.h>
  24 #include <linux/rtc.h>
  25 #include <linux/vt_kern.h>
  26 #include <linux/bcd.h>
  27
  28 #include <asm/io.h>
  29 #include <asm/rtc.h>
  30 #include <asm/bootinfo.h>
  31 #include <asm/system.h>
  32 #include <asm/pgtable.h>
  33 #include <asm/setup.h>
  34 #include <asm/irq.h>
  35 #include <asm/traps.h>
  36 #include <asm/machdep.h>
  37 #include <asm/q40_master.h>
  38
  39 extern irqreturn_t q40_process_int(int level, struct pt_regs *regs);
  40 extern void q40_init_IRQ(void);
  41 static void q40_get_model(char *model);
  42 static int  q40_get_hardware_list(char *buffer);
  43 extern void q40_sched_init(irq_handler_t handler);
  44
  45 static unsigned long q40_gettimeoffset(void);
  46 static int q40_hwclk(int, struct rtc_time *);
  47 static unsigned int q40_get_ss(void);
  48 static int q40_set_clock_mmss(unsigned long);
  49 static int q40_get_rtc_pll(struct rtc_pll_info *pll);
  50 static int q40_set_rtc_pll(struct rtc_pll_info *pll);
  51 extern void q40_waitbut(void);
  52 void q40_set_vectors(void);
  53
  54 extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/);
  55
  56 static void q40_mem_console_write(struct console *co, const char *b,
  57                                   unsigned int count);
  58
  59 extern int ql_ticks;
  60
  61 static struct console q40_console_driver = {
  62         .name   = "debug",
  63         .write  = q40_mem_console_write,
  64         .flags  = CON_PRINTBUFFER,
  65         .index  = -1,
  66 };
  67
  68
  69 /* early debugging function:*/
  70 extern char *q40_mem_cptr; /*=(char *)0xff020000;*/
  71 static int _cpleft;
  72
  73 static void q40_mem_console_write(struct console *co, const char *s,
  74                                   unsigned int count)
  75 {
  76         const char *p = s;
  77
  78         if (count < _cpleft) {
  79                 while (count-- > 0) {
  80                         *q40_mem_cptr = *p++;
  81                         q40_mem_cptr += 4;
  82                         _cpleft--;
  83                 }
  84         }
  85 }
  86
  87 static int __init q40_debug_setup(char *arg)
  88 {
  89         /* useful for early debugging stages - writes kernel messages into SRAM */
  90         if (MACH_IS_Q40 && !strncmp(arg, "mem", 3)) {
  91                 /*printk("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/
  92                 _cpleft = 2000 - ((long)q40_mem_cptr-0xff020000) / 4;
  93                 register_console(&q40_console_driver);
  94         }
  95         return 0;
  96 }
  97
  98 early_param("debug", q40_debug_setup);
  99
 100 #if 0
 101 void printq40(char *str)
 102 {
 103         int l = strlen(str);
 104         char *p = q40_mem_cptr;
 105
 106         while (l-- > 0 && _cpleft-- > 0) {
 107                 *p = *str++;
 108                 p += 4;
 109         }
 110         q40_mem_cptr = p;
 111 }
 112 #endif
 113
 114 static int halted;
 115
 116 #ifdef CONFIG_HEARTBEAT
 117 static void q40_heartbeat(int on)
 118 {
 119         if (halted)
 120                 return;
 121
 122         if (on)
 123                 Q40_LED_ON();
 124         else
 125                 Q40_LED_OFF();
 126 }
 127 #endif
 128
 129 static void q40_reset(void)
 130 {
 131         halted = 1;
 132         printk("\n\n*******************************************\n"
 133                 "Called q40_reset : press the RESET button!! \n"
 134                 "*******************************************\n");
 135         Q40_LED_ON();
 136         while (1)
 137                 ;
 138 }
 139
 140 static void q40_halt(void)
 141 {
 142         halted = 1;
 143         printk("\n\n*******************\n"
 144                    "  Called q40_halt\n"
 145                    "*******************\n");
 146         Q40_LED_ON();
 147         while (1)
 148                 ;
 149 }
 150
 151 static void q40_get_model(char *model)
 152 {
 153         sprintf(model, "Q40");
 154 }
 155
 156 /* No hardware options on Q40? */
 157
 158 static int q40_get_hardware_list(char *buffer)
 159 {
 160         *buffer = '\0';
 161         return 0;
 162 }
 163
 164 static unsigned int serports[] =
 165 {
 166         0x3f8,0x2f8,0x3e8,0x2e8,0
 167 };
 168
 169 static void q40_disable_irqs(void)
 170 {
 171         unsigned i, j;
 172
 173         j = 0;
 174         while ((i = serports[j++]))
 175                 outb(0, i + UART_IER);
 176         master_outb(0, EXT_ENABLE_REG);
 177         master_outb(0, KEY_IRQ_ENABLE_REG);
 178 }
 179
 180 void __init config_q40(void)
 181 {
 182         mach_sched_init = q40_sched_init;
 183
 184         mach_init_IRQ = q40_init_IRQ;
 185         mach_gettimeoffset = q40_gettimeoffset;
 186         mach_hwclk = q40_hwclk;
 187         mach_get_ss = q40_get_ss;
 188         mach_get_rtc_pll = q40_get_rtc_pll;
 189         mach_set_rtc_pll = q40_set_rtc_pll;
 190         mach_set_clock_mmss = q40_set_clock_mmss;
 191
 192         mach_reset = q40_reset;
 193         mach_get_model = q40_get_model;
 194         mach_get_hardware_list = q40_get_hardware_list;
 195
 196 #if defined(CONFIG_INPUT_M68K_BEEP) || defined(CONFIG_INPUT_M68K_BEEP_MODULE)
 197         mach_beep = q40_mksound;
 198 #endif
 199 #ifdef CONFIG_HEARTBEAT
 200         mach_heartbeat = q40_heartbeat;
 201 #endif
 202         mach_halt = q40_halt;
 203
 204         /* disable a few things that SMSQ might have left enabled */
 205         q40_disable_irqs();
 206
 207         /* no DMA at all, but ide-scsi requires it.. make sure
 208          * all physical RAM fits into the boundary - otherwise
 209          * allocator may play costly and useless tricks */
 210         mach_max_dma_address = 1024*1024*1024;
 211 }
 212
 213
 214 int q40_parse_bootinfo(const struct bi_record *rec)
 215 {
 216         return 1;
 217 }
 218
 219
 220 static unsigned long q40_gettimeoffset(void)
 221 {
 222         return 5000 * (ql_ticks != 0);
 223 }
 224
 225
 226 /*
 227  * Looks like op is non-zero for setting the clock, and zero for
 228  * reading the clock.
 229  *
 230  *  struct hwclk_time {
 231  *         unsigned        sec;       0..59
 232  *         unsigned        min;       0..59
 233  *         unsigned        hour;      0..23
 234  *         unsigned        day;       1..31
 235  *         unsigned        mon;       0..11
 236  *         unsigned        year;      00...
 237  *         int             wday;      0..6, 0 is Sunday, -1 means unknown/don't set
 238  * };
 239  */
 240
 241 static int q40_hwclk(int op, struct rtc_time *t)
 242 {
 243         if (op) {
 244                 /* Write.... */
 245                 Q40_RTC_CTRL |= Q40_RTC_WRITE;
 246
 247                 Q40_RTC_SECS = bin2bcd(t->tm_sec);
 248                 Q40_RTC_MINS = bin2bcd(t->tm_min);
 249                 Q40_RTC_HOUR = bin2bcd(t->tm_hour);
 250                 Q40_RTC_DATE = bin2bcd(t->tm_mday);
 251                 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1);
 252                 Q40_RTC_YEAR = bin2bcd(t->tm_year%100);
 253                 if (t->tm_wday >= 0)
 254                         Q40_RTC_DOW = bin2bcd(t->tm_wday+1);
 255
 256                 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
 257         } else {
 258                 /* Read....  */
 259                 Q40_RTC_CTRL |= Q40_RTC_READ;
 260
 261                 t->tm_year = bcd2bin (Q40_RTC_YEAR);
 262                 t->tm_mon  = bcd2bin (Q40_RTC_MNTH)-1;
 263                 t->tm_mday = bcd2bin (Q40_RTC_DATE);
 264                 t->tm_hour = bcd2bin (Q40_RTC_HOUR);
 265                 t->tm_min  = bcd2bin (Q40_RTC_MINS);
 266                 t->tm_sec  = bcd2bin (Q40_RTC_SECS);
 267
 268                 Q40_RTC_CTRL &= ~(Q40_RTC_READ);
 269
 270                 if (t->tm_year < 70)
 271                         t->tm_year += 100;
 272                 t->tm_wday = bcd2bin(Q40_RTC_DOW)-1;
 273         }
 274
 275         return 0;
 276 }
 277
 278 static unsigned int q40_get_ss(void)
 279 {
 280         return bcd2bin(Q40_RTC_SECS);
 281 }
 282
 283 /*
 284  * Set the minutes and seconds from seconds value 'nowtime'.  Fail if
 285  * clock is out by > 30 minutes.  Logic lifted from atari code.
 286  */
 287
 288 static int q40_set_clock_mmss(unsigned long nowtime)
 289 {
 290         int retval = 0;
 291         short real_seconds = nowtime % 60, real_minutes = (nowtime / 60) % 60;
 292
 293         int rtc_minutes;
 294
 295         rtc_minutes = bcd2bin(Q40_RTC_MINS);
 296
 297         if ((rtc_minutes < real_minutes ?
 298              real_minutes - rtc_minutes :
 299              rtc_minutes - real_minutes) < 30) {
 300                 Q40_RTC_CTRL |= Q40_RTC_WRITE;
 301                 Q40_RTC_MINS = bin2bcd(real_minutes);
 302                 Q40_RTC_SECS = bin2bcd(real_seconds);
 303                 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
 304         } else
 305                 retval = -1;
 306
 307         return retval;
 308 }
 309
 310
 311 /* get and set PLL calibration of RTC clock */
 312 #define Q40_RTC_PLL_MASK ((1<<5)-1)
 313 #define Q40_RTC_PLL_SIGN (1<<5)
 314
 315 static int q40_get_rtc_pll(struct rtc_pll_info *pll)
 316 {
 317         int tmp = Q40_RTC_CTRL;
 318
 319         pll->pll_value = tmp & Q40_RTC_PLL_MASK;
 320         if (tmp & Q40_RTC_PLL_SIGN)
 321                 pll->pll_value = -pll->pll_value;
 322         pll->pll_max = 31;
 323         pll->pll_min = -31;
 324         pll->pll_posmult = 512;
 325         pll->pll_negmult = 256;
 326         pll->pll_clock = 125829120;
 327
 328         return 0;
 329 }
 330
 331 static int q40_set_rtc_pll(struct rtc_pll_info *pll)
 332 {
 333         if (!pll->pll_ctrl) {
 334                 /* the docs are a bit unclear so I am doublesetting */
 335                 /* RTC_WRITE here ... */
 336                 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) |
 337                           Q40_RTC_WRITE;
 338                 Q40_RTC_CTRL |= Q40_RTC_WRITE;
 339                 Q40_RTC_CTRL = tmp;
 340                 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
 341                 return 0;
 342         } else
 343                 return -EINVAL;
 344 }