arch/ia64/sn/kernel/sn2/sn2_smp.c

   1 /*
   2  * SN2 Platform specific SMP Support
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 2000-2006 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/threads.h>
  15 #include <linux/sched.h>
  16 #include <linux/smp.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/irq.h>
  19 #include <linux/mmzone.h>
  20 #include <linux/module.h>
  21 #include <linux/bitops.h>
  22 #include <linux/nodemask.h>
  23 #include <linux/proc_fs.h>
  24 #include <linux/seq_file.h>
  25
  26 #include <asm/processor.h>
  27 #include <asm/irq.h>
  28 #include <asm/sal.h>
  29 #include <asm/system.h>
  30 #include <asm/delay.h>
  31 #include <asm/io.h>
  32 #include <asm/smp.h>
  33 #include <asm/tlb.h>
  34 #include <asm/numa.h>
  35 #include <asm/hw_irq.h>
  36 #include <asm/current.h>
  37 #include <asm/sn/sn_cpuid.h>
  38 #include <asm/sn/sn_sal.h>
  39 #include <asm/sn/addrs.h>
  40 #include <asm/sn/shub_mmr.h>
  41 #include <asm/sn/nodepda.h>
  42 #include <asm/sn/rw_mmr.h>
  43
  44 DEFINE_PER_CPU(struct ptc_stats, ptcstats);
  45 DECLARE_PER_CPU(struct ptc_stats, ptcstats);
  46
  47 static  __cacheline_aligned DEFINE_SPINLOCK(sn2_global_ptc_lock);
  48
  49 void sn2_ptc_deadlock_recovery(short *, short, int, volatile unsigned long *, unsigned long data0,
  50         volatile unsigned long *, unsigned long data1);
  51
  52 #ifdef DEBUG_PTC
  53 /*
  54  * ptctest:
  55  *
  56  *      xyz - 3 digit hex number:
  57  *              x - Force PTC purges to use shub:
  58  *                      0 - no force
  59  *                      1 - force
  60  *              y - interupt enable
  61  *                      0 - disable interrupts
  62  *                      1 - leave interuupts enabled
  63  *              z - type of lock:
  64  *                      0 - global lock
  65  *                      1 - node local lock
  66  *                      2 - no lock
  67  *
  68  *      Note: on shub1, only ptctest == 0 is supported. Don't try other values!
  69  */
  70
  71 static unsigned int sn2_ptctest = 0;
  72
  73 static int __init ptc_test(char *str)
  74 {
  75         get_option(&str, &sn2_ptctest);
  76         return 1;
  77 }
  78 __setup("ptctest=", ptc_test);
  79
  80 static inline int ptc_lock(unsigned long *flagp)
  81 {
  82         unsigned long opt = sn2_ptctest & 255;
  83
  84         switch (opt) {
  85         case 0x00:
  86                 spin_lock_irqsave(&sn2_global_ptc_lock, *flagp);
  87                 break;
  88         case 0x01:
  89                 spin_lock_irqsave(&sn_nodepda->ptc_lock, *flagp);
  90                 break;
  91         case 0x02:
  92                 local_irq_save(*flagp);
  93                 break;
  94         case 0x10:
  95                 spin_lock(&sn2_global_ptc_lock);
  96                 break;
  97         case 0x11:
  98                 spin_lock(&sn_nodepda->ptc_lock);
  99                 break;
 100         case 0x12:
 101                 break;
 102         default:
 103                 BUG();
 104         }
 105         return opt;
 106 }
 107
 108 static inline void ptc_unlock(unsigned long flags, int opt)
 109 {
 110         switch (opt) {
 111         case 0x00:
 112                 spin_unlock_irqrestore(&sn2_global_ptc_lock, flags);
 113                 break;
 114         case 0x01:
 115                 spin_unlock_irqrestore(&sn_nodepda->ptc_lock, flags);
 116                 break;
 117         case 0x02:
 118                 local_irq_restore(flags);
 119                 break;
 120         case 0x10:
 121                 spin_unlock(&sn2_global_ptc_lock);
 122                 break;
 123         case 0x11:
 124                 spin_unlock(&sn_nodepda->ptc_lock);
 125                 break;
 126         case 0x12:
 127                 break;
 128         default:
 129                 BUG();
 130         }
 131 }
 132 #else
 133
 134 #define sn2_ptctest     0
 135
 136 static inline int ptc_lock(unsigned long *flagp)
 137 {
 138         spin_lock_irqsave(&sn2_global_ptc_lock, *flagp);
 139         return 0;
 140 }
 141
 142 static inline void ptc_unlock(unsigned long flags, int opt)
 143 {
 144         spin_unlock_irqrestore(&sn2_global_ptc_lock, flags);
 145 }
 146 #endif
 147
 148 struct ptc_stats {
 149         unsigned long ptc_l;
 150         unsigned long change_rid;
 151         unsigned long shub_ptc_flushes;
 152         unsigned long nodes_flushed;
 153         unsigned long deadlocks;
 154         unsigned long lock_itc_clocks;
 155         unsigned long shub_itc_clocks;
 156         unsigned long shub_itc_clocks_max;
 157 };
 158
 159 static inline unsigned long wait_piowc(void)
 160 {
 161         volatile unsigned long *piows, zeroval;
 162         unsigned long ws;
 163
 164         piows = pda->pio_write_status_addr;
 165         zeroval = pda->pio_write_status_val;
 166         do {
 167                 cpu_relax();
 168         } while (((ws = *piows) & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK) != zeroval);
 169         return ws;
 170 }
 171
 172 /**
 173  * sn_migrate - SN-specific task migration actions
 174  * @task: Task being migrated to new CPU
 175  *
 176  * SN2 PIO writes from separate CPUs are not guaranteed to arrive in order.
 177  * Context switching user threads which have memory-mapped MMIO may cause
 178  * PIOs to issue from seperate CPUs, thus the PIO writes must be drained
 179  * from the previous CPU's Shub before execution resumes on the new CPU.
 180  */
 181 void sn_migrate(struct task_struct *task)
 182 {
 183         pda_t *last_pda = pdacpu(task_thread_info(task)->last_cpu);
 184         volatile unsigned long *adr = last_pda->pio_write_status_addr;
 185         unsigned long val = last_pda->pio_write_status_val;
 186
 187         /* Drain PIO writes from old CPU's Shub */
 188         while (unlikely((*adr & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK)
 189                         != val))
 190                 cpu_relax();
 191 }
 192
 193 void sn_tlb_migrate_finish(struct mm_struct *mm)
 194 {
 195         if (mm == current->mm)
 196                 flush_tlb_mm(mm);
 197 }
 198
 199 /**
 200  * sn2_global_tlb_purge - globally purge translation cache of virtual address range
 201  * @mm: mm_struct containing virtual address range
 202  * @start: start of virtual address range
 203  * @end: end of virtual address range
 204  * @nbits: specifies number of bytes to purge per instruction (num = 1<<(nbits & 0xfc))
 205  *
 206  * Purges the translation caches of all processors of the given virtual address
 207  * range.
 208  *
 209  * Note:
 210  *      - cpu_vm_mask is a bit mask that indicates which cpus have loaded the context.
 211  *      - cpu_vm_mask is converted into a nodemask of the nodes containing the
 212  *        cpus in cpu_vm_mask.
 213  *      - if only one bit is set in cpu_vm_mask & it is the current cpu & the
 214  *        process is purging its own virtual address range, then only the
 215  *        local TLB needs to be flushed. This flushing can be done using
 216  *        ptc.l. This is the common case & avoids the global spinlock.
 217  *      - if multiple cpus have loaded the context, then flushing has to be
 218  *        done with ptc.g/MMRs under protection of the global ptc_lock.
 219  */
 220
 221 void
 222 sn2_global_tlb_purge(struct mm_struct *mm, unsigned long start,
 223                      unsigned long end, unsigned long nbits)
 224 {
 225         int i, opt, shub1, cnode, mynasid, cpu, lcpu = 0, nasid, flushed = 0;
 226         int mymm = (mm == current->active_mm && current->mm);
 227         volatile unsigned long *ptc0, *ptc1;
 228         unsigned long itc, itc2, flags, data0 = 0, data1 = 0, rr_value;
 229         short nasids[MAX_NUMNODES], nix;
 230         nodemask_t nodes_flushed;
 231
 232         nodes_clear(nodes_flushed);
 233         i = 0;
 234
 235         for_each_cpu_mask(cpu, mm->cpu_vm_mask) {
 236                 cnode = cpu_to_node(cpu);
 237                 node_set(cnode, nodes_flushed);
 238                 lcpu = cpu;
 239                 i++;
 240         }
 241
 242         if (i == 0)
 243                 return;
 244
 245         preempt_disable();
 246
 247         if (likely(i == 1 && lcpu == smp_processor_id() && mymm)) {
 248                 do {
 249                         ia64_ptcl(start, nbits << 2);
 250                         start += (1UL << nbits);
 251                 } while (start < end);
 252                 ia64_srlz_i();
 253                 __get_cpu_var(ptcstats).ptc_l++;
 254                 preempt_enable();
 255                 return;
 256         }
 257
 258         if (atomic_read(&mm->mm_users) == 1 && mymm) {
 259                 flush_tlb_mm(mm);
 260                 __get_cpu_var(ptcstats).change_rid++;
 261                 preempt_enable();
 262                 return;
 263         }
 264
 265         itc = ia64_get_itc();
 266         nix = 0;
 267         for_each_node_mask(cnode, nodes_flushed)
 268                 nasids[nix++] = cnodeid_to_nasid(cnode);
 269
 270         rr_value = (mm->context << 3) | REGION_NUMBER(start);
 271
 272         shub1 = is_shub1();
 273         if (shub1) {
 274                 data0 = (1UL << SH1_PTC_0_A_SHFT) |
 275                         (nbits << SH1_PTC_0_PS_SHFT) |
 276                         (rr_value << SH1_PTC_0_RID_SHFT) |
 277                         (1UL << SH1_PTC_0_START_SHFT);
 278                 ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_0);
 279                 ptc1 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_1);
 280         } else {
 281                 data0 = (1UL << SH2_PTC_A_SHFT) |
 282                         (nbits << SH2_PTC_PS_SHFT) |
 283                         (1UL << SH2_PTC_START_SHFT);
 284                 ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH2_PTC +
 285                         (rr_value << SH2_PTC_RID_SHFT));
 286                 ptc1 = NULL;
 287         }
 288
 289
 290         mynasid = get_nasid();
 291
 292         itc = ia64_get_itc();
 293         opt = ptc_lock(&flags);
 294         itc2 = ia64_get_itc();
 295         __get_cpu_var(ptcstats).lock_itc_clocks += itc2 - itc;
 296         __get_cpu_var(ptcstats).shub_ptc_flushes++;
 297         __get_cpu_var(ptcstats).nodes_flushed += nix;
 298
 299         do {
 300                 if (shub1)
 301                         data1 = start | (1UL << SH1_PTC_1_START_SHFT);
 302                 else
 303                         data0 = (data0 & ~SH2_PTC_ADDR_MASK) | (start & SH2_PTC_ADDR_MASK);
 304                 for (i = 0; i < nix; i++) {
 305                         nasid = nasids[i];
 306                         if ((!(sn2_ptctest & 3)) && unlikely(nasid == mynasid && mymm)) {
 307                                 ia64_ptcga(start, nbits << 2);
 308                                 ia64_srlz_i();
 309                         } else {
 310                                 ptc0 = CHANGE_NASID(nasid, ptc0);
 311                                 if (ptc1)
 312                                         ptc1 = CHANGE_NASID(nasid, ptc1);
 313                                 pio_atomic_phys_write_mmrs(ptc0, data0, ptc1,
 314                                                            data1);
 315                                 flushed = 1;
 316                         }
 317                 }
 318                 if (flushed
 319                     && (wait_piowc() &
 320                                 (SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK))) {
 321                         sn2_ptc_deadlock_recovery(nasids, nix, mynasid, ptc0, data0, ptc1, data1);
 322                 }
 323
 324                 start += (1UL << nbits);
 325
 326         } while (start < end);
 327
 328         itc2 = ia64_get_itc() - itc2;
 329         __get_cpu_var(ptcstats).shub_itc_clocks += itc2;
 330         if (itc2 > __get_cpu_var(ptcstats).shub_itc_clocks_max)
 331                 __get_cpu_var(ptcstats).shub_itc_clocks_max = itc2;
 332
 333         ptc_unlock(flags, opt);
 334
 335         preempt_enable();
 336 }
 337
 338 /*
 339  * sn2_ptc_deadlock_recovery
 340  *
 341  * Recover from PTC deadlocks conditions. Recovery requires stepping thru each
 342  * TLB flush transaction.  The recovery sequence is somewhat tricky & is
 343  * coded in assembly language.
 344  */
 345 void sn2_ptc_deadlock_recovery(short *nasids, short nix, int mynasid, volatile unsigned long *ptc0, unsigned long data0,
 346         volatile unsigned long *ptc1, unsigned long data1)
 347 {
 348         extern void sn2_ptc_deadlock_recovery_core(volatile unsigned long *, unsigned long,
 349                 volatile unsigned long *, unsigned long, volatile unsigned long *, unsigned long);
 350         short nasid, i;
 351         unsigned long *piows, zeroval;
 352
 353         __get_cpu_var(ptcstats).deadlocks++;
 354
 355         piows = (unsigned long *) pda->pio_write_status_addr;
 356         zeroval = pda->pio_write_status_val;
 357
 358         for (i=0; i < nix; i++) {
 359                 nasid = nasids[i];
 360                 if (!(sn2_ptctest & 3) && nasid == mynasid)
 361                         continue;
 362                 ptc0 = CHANGE_NASID(nasid, ptc0);
 363                 if (ptc1)
 364                         ptc1 = CHANGE_NASID(nasid, ptc1);
 365                 sn2_ptc_deadlock_recovery_core(ptc0, data0, ptc1, data1, piows, zeroval);
 366         }
 367
 368 }
 369
 370 /**
 371  * sn_send_IPI_phys - send an IPI to a Nasid and slice
 372  * @nasid: nasid to receive the interrupt (may be outside partition)
 373  * @physid: physical cpuid to receive the interrupt.
 374  * @vector: command to send
 375  * @delivery_mode: delivery mechanism
 376  *
 377  * Sends an IPI (interprocessor interrupt) to the processor specified by
 378  * @physid
 379  *
 380  * @delivery_mode can be one of the following
 381  *
 382  * %IA64_IPI_DM_INT - pend an interrupt
 383  * %IA64_IPI_DM_PMI - pend a PMI
 384  * %IA64_IPI_DM_NMI - pend an NMI
 385  * %IA64_IPI_DM_INIT - pend an INIT interrupt
 386  */
 387 void sn_send_IPI_phys(int nasid, long physid, int vector, int delivery_mode)
 388 {
 389         long val;
 390         unsigned long flags = 0;
 391         volatile long *p;
 392
 393         p = (long *)GLOBAL_MMR_PHYS_ADDR(nasid, SH_IPI_INT);
 394         val = (1UL << SH_IPI_INT_SEND_SHFT) |
 395             (physid << SH_IPI_INT_PID_SHFT) |
 396             ((long)delivery_mode << SH_IPI_INT_TYPE_SHFT) |
 397             ((long)vector << SH_IPI_INT_IDX_SHFT) |
 398             (0x000feeUL << SH_IPI_INT_BASE_SHFT);
 399
 400         mb();
 401         if (enable_shub_wars_1_1()) {
 402                 spin_lock_irqsave(&sn2_global_ptc_lock, flags);
 403         }
 404         pio_phys_write_mmr(p, val);
 405         if (enable_shub_wars_1_1()) {
 406                 wait_piowc();
 407                 spin_unlock_irqrestore(&sn2_global_ptc_lock, flags);
 408         }
 409
 410 }
 411
 412 EXPORT_SYMBOL(sn_send_IPI_phys);
 413
 414 /**
 415  * sn2_send_IPI - send an IPI to a processor
 416  * @cpuid: target of the IPI
 417  * @vector: command to send
 418  * @delivery_mode: delivery mechanism
 419  * @redirect: redirect the IPI?
 420  *
 421  * Sends an IPI (InterProcessor Interrupt) to the processor specified by
 422  * @cpuid.  @vector specifies the command to send, while @delivery_mode can
 423  * be one of the following
 424  *
 425  * %IA64_IPI_DM_INT - pend an interrupt
 426  * %IA64_IPI_DM_PMI - pend a PMI
 427  * %IA64_IPI_DM_NMI - pend an NMI
 428  * %IA64_IPI_DM_INIT - pend an INIT interrupt
 429  */
 430 void sn2_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
 431 {
 432         long physid;
 433         int nasid;
 434
 435         physid = cpu_physical_id(cpuid);
 436         nasid = cpuid_to_nasid(cpuid);
 437
 438         /* the following is used only when starting cpus at boot time */
 439         if (unlikely(nasid == -1))
 440                 ia64_sn_get_sapic_info(physid, &nasid, NULL, NULL);
 441
 442         sn_send_IPI_phys(nasid, physid, vector, delivery_mode);
 443 }
 444
 445 #ifdef CONFIG_PROC_FS
 446
 447 #define PTC_BASENAME    "sgi_sn/ptc_statistics"
 448
 449 static void *sn2_ptc_seq_start(struct seq_file *file, loff_t * offset)
 450 {
 451         if (*offset < NR_CPUS)
 452                 return offset;
 453         return NULL;
 454 }
 455
 456 static void *sn2_ptc_seq_next(struct seq_file *file, void *data, loff_t * offset)
 457 {
 458         (*offset)++;
 459         if (*offset < NR_CPUS)
 460                 return offset;
 461         return NULL;
 462 }
 463
 464 static void sn2_ptc_seq_stop(struct seq_file *file, void *data)
 465 {
 466 }
 467
 468 static int sn2_ptc_seq_show(struct seq_file *file, void *data)
 469 {
 470         struct ptc_stats *stat;
 471         int cpu;
 472
 473         cpu = *(loff_t *) data;
 474
 475         if (!cpu) {
 476                 seq_printf(file, "# ptc_l change_rid shub_ptc_flushes shub_nodes_flushed deadlocks lock_nsec shub_nsec shub_nsec_max\n");
 477                 seq_printf(file, "# ptctest %d\n", sn2_ptctest);
 478         }
 479
 480         if (cpu < NR_CPUS && cpu_online(cpu)) {
 481                 stat = &per_cpu(ptcstats, cpu);
 482                 seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld %ld\n", cpu, stat->ptc_l,
 483                                 stat->change_rid, stat->shub_ptc_flushes, stat->nodes_flushed,
 484                                 stat->deadlocks,
 485                                 1000 * stat->lock_itc_clocks / per_cpu(cpu_info, cpu).cyc_per_usec,
 486                                 1000 * stat->shub_itc_clocks / per_cpu(cpu_info, cpu).cyc_per_usec,
 487                                 1000 * stat->shub_itc_clocks_max / per_cpu(cpu_info, cpu).cyc_per_usec);
 488         }
 489
 490         return 0;
 491 }
 492
 493 static struct seq_operations sn2_ptc_seq_ops = {
 494         .start = sn2_ptc_seq_start,
 495         .next = sn2_ptc_seq_next,
 496         .stop = sn2_ptc_seq_stop,
 497         .show = sn2_ptc_seq_show
 498 };
 499
 500 int sn2_ptc_proc_open(struct inode *inode, struct file *file)
 501 {
 502         return seq_open(file, &sn2_ptc_seq_ops);
 503 }
 504
 505 static struct file_operations proc_sn2_ptc_operations = {
 506         .open = sn2_ptc_proc_open,
 507         .read = seq_read,
 508         .llseek = seq_lseek,
 509         .release = seq_release,
 510 };
 511
 512 static struct proc_dir_entry *proc_sn2_ptc;
 513
 514 static int __init sn2_ptc_init(void)
 515 {
 516         if (!ia64_platform_is("sn2"))
 517                 return -ENOSYS;
 518
 519         if (!(proc_sn2_ptc = create_proc_entry(PTC_BASENAME, 0444, NULL))) {
 520                 printk(KERN_ERR "unable to create %s proc entry", PTC_BASENAME);
 521                 return -EINVAL;
 522         }
 523         proc_sn2_ptc->proc_fops = &proc_sn2_ptc_operations;
 524         spin_lock_init(&sn2_global_ptc_lock);
 525         return 0;
 526 }
 527
 528 static void __exit sn2_ptc_exit(void)
 529 {
 530         remove_proc_entry(PTC_BASENAME, NULL);
 531 }
 532
 533 module_init(sn2_ptc_init);
 534 module_exit(sn2_ptc_exit);
 535 #endif /* CONFIG_PROC_FS */
 536