4 * Prints processor specific information reported by PAL.
5 * This code is based on specification of PAL as of the
6 * Intel IA-64 Architecture Software Developer's Manual v1.0.
9 * Copyright (C) 2000-2001, 2003 Hewlett-Packard Co
10 * Stephane Eranian <eranian@hpl.hp.com>
11 * Copyright (C) 2004 Intel Corporation
12 * Ashok Raj <ashok.raj@intel.com>
14 * 05/26/2000 S.Eranian initial release
15 * 08/21/2000 S.Eranian updated to July 2000 PAL specs
16 * 02/05/2001 S.Eranian fixed module support
17 * 10/23/2001 S.Eranian updated pal_perf_mon_info bug fixes
18 * 03/24/2004 Ashok Raj updated to work with CPU Hotplug
19 * 10/26/2006 Russ Anderson updated processor features to rev 2.2 spec
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/init.h>
24 #include <linux/proc_fs.h>
26 #include <linux/module.h>
27 #include <linux/efi.h>
28 #include <linux/notifier.h>
29 #include <linux/cpu.h>
30 #include <linux/cpumask.h>
35 #include <asm/processor.h>
36 #include <linux/smp.h>
38 MODULE_AUTHOR("Stephane Eranian <eranian@hpl.hp.com>");
39 MODULE_DESCRIPTION("/proc interface to IA-64 PAL");
40 MODULE_LICENSE("GPL");
42 #define PALINFO_VERSION "0.5"
44 typedef int (*palinfo_func_t)(char*);
47 const char *name; /* name of the proc entry */
48 palinfo_func_t proc_read; /* function to call for reading */
49 struct proc_dir_entry *entry; /* registered entry (removal) */
54 * A bunch of string array to get pretty printing
57 static char *cache_types[] = {
61 "Data/Instruction" /* unified */
64 static const char *cache_mattrib[]={
71 static const char *cache_st_hints[]={
75 "Non-temporal, all levels",
82 static const char *cache_ld_hints[]={
84 "Non-temporal, level 1",
86 "Non-temporal, all levels",
93 static const char *rse_hints[]={
97 "eager loads and stores"
100 #define RSE_HINTS_COUNT ARRAY_SIZE(rse_hints)
102 static const char *mem_attrib[]={
114 * Take a 64bit vector and produces a string such that
115 * if bit n is set then 2^n in clear text is generated. The adjustment
116 * to the right unit is also done.
119 * - a pointer to a buffer to hold the string
122 * - a pointer to the end of the buffer
126 bitvector_process(char *p, u64 vector)
129 const char *units[]={ "", "K", "M", "G", "T" };
131 for (i=0, j=0; i < 64; i++ , j=i/10) {
133 p += sprintf(p, "%d%s ", 1 << (i-j*10), units[j]);
141 * Take a 64bit vector and produces a string such that
142 * if bit n is set then register n is present. The function
143 * takes into account consecutive registers and prints out ranges.
146 * - a pointer to a buffer to hold the string
149 * - a pointer to the end of the buffer
153 bitregister_process(char *p, u64 *reg_info, int max)
155 int i, begin, skip = 0;
156 u64 value = reg_info[0];
158 value >>= i = begin = ffs(value) - 1;
160 for(; i < max; i++ ) {
162 if (i != 0 && (i%64) == 0) value = *++reg_info;
164 if ((value & 0x1) == 0 && skip == 0) {
166 p += sprintf(p, "%d-%d ", begin, i-1);
168 p += sprintf(p, "%d ", i-1);
171 } else if ((value & 0x1) && skip == 1) {
179 p += sprintf(p, "%d-127", begin);
181 p += sprintf(p, "127");
188 power_info(char *page)
192 u64 halt_info_buffer[8];
193 pal_power_mgmt_info_u_t *halt_info =(pal_power_mgmt_info_u_t *)halt_info_buffer;
196 status = ia64_pal_halt_info(halt_info);
197 if (status != 0) return 0;
199 for (i=0; i < 8 ; i++ ) {
200 if (halt_info[i].pal_power_mgmt_info_s.im == 1) {
201 p += sprintf(p, "Power level %d:\n"
202 "\tentry_latency : %d cycles\n"
203 "\texit_latency : %d cycles\n"
204 "\tpower consumption : %d mW\n"
205 "\tCache+TLB coherency : %s\n", i,
206 halt_info[i].pal_power_mgmt_info_s.entry_latency,
207 halt_info[i].pal_power_mgmt_info_s.exit_latency,
208 halt_info[i].pal_power_mgmt_info_s.power_consumption,
209 halt_info[i].pal_power_mgmt_info_s.co ? "Yes" : "No");
211 p += sprintf(p,"Power level %d: not implemented\n",i);
218 cache_info(char *page)
221 u64 i, levels, unique_caches;
222 pal_cache_config_info_t cci;
226 if ((status = ia64_pal_cache_summary(&levels, &unique_caches)) != 0) {
227 printk(KERN_ERR "ia64_pal_cache_summary=%ld\n", status);
231 p += sprintf(p, "Cache levels : %ld\nUnique caches : %ld\n\n", levels, unique_caches);
233 for (i=0; i < levels; i++) {
235 for (j=2; j >0 ; j--) {
237 /* even without unification some level may not be present */
238 if ((status=ia64_pal_cache_config_info(i,j, &cci)) != 0) {
242 "%s Cache level %lu:\n"
243 "\tSize : %u bytes\n"
245 cache_types[j+cci.pcci_unified], i+1,
246 cci.pcci_cache_size);
248 if (cci.pcci_unified) p += sprintf(p, "Unified ");
250 p += sprintf(p, "%s\n", cache_mattrib[cci.pcci_cache_attr]);
253 "\tAssociativity : %d\n"
254 "\tLine size : %d bytes\n"
255 "\tStride : %d bytes\n",
256 cci.pcci_assoc, 1<<cci.pcci_line_size, 1<<cci.pcci_stride);
258 p += sprintf(p, "\tStore latency : N/A\n");
260 p += sprintf(p, "\tStore latency : %d cycle(s)\n",
261 cci.pcci_st_latency);
264 "\tLoad latency : %d cycle(s)\n"
265 "\tStore hints : ", cci.pcci_ld_latency);
267 for(k=0; k < 8; k++ ) {
268 if ( cci.pcci_st_hints & 0x1)
269 p += sprintf(p, "[%s]", cache_st_hints[k]);
270 cci.pcci_st_hints >>=1;
272 p += sprintf(p, "\n\tLoad hints : ");
274 for(k=0; k < 8; k++ ) {
275 if (cci.pcci_ld_hints & 0x1)
276 p += sprintf(p, "[%s]", cache_ld_hints[k]);
277 cci.pcci_ld_hints >>=1;
280 "\n\tAlias boundary : %d byte(s)\n"
283 1<<cci.pcci_alias_boundary, cci.pcci_tag_lsb,
286 /* when unified, data(j=2) is enough */
287 if (cci.pcci_unified) break;
298 u64 tr_pages =0, vw_pages=0, tc_pages;
300 pal_vm_info_1_u_t vm_info_1;
301 pal_vm_info_2_u_t vm_info_2;
302 pal_tc_info_u_t tc_info;
303 ia64_ptce_info_t ptce;
308 if ((status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2)) !=0) {
309 printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
313 "Physical Address Space : %d bits\n"
314 "Virtual Address Space : %d bits\n"
315 "Protection Key Registers(PKR) : %d\n"
316 "Implemented bits in PKR.key : %d\n"
317 "Hash Tag ID : 0x%x\n"
318 "Size of RR.rid : %d\n",
319 vm_info_1.pal_vm_info_1_s.phys_add_size,
320 vm_info_2.pal_vm_info_2_s.impl_va_msb+1,
321 vm_info_1.pal_vm_info_1_s.max_pkr+1,
322 vm_info_1.pal_vm_info_1_s.key_size,
323 vm_info_1.pal_vm_info_1_s.hash_tag_id,
324 vm_info_2.pal_vm_info_2_s.rid_size);
327 if (ia64_pal_mem_attrib(&attrib) == 0) {
328 p += sprintf(p, "Supported memory attributes : ");
330 for (i = 0; i < 8; i++) {
331 if (attrib & (1 << i)) {
332 p += sprintf(p, "%s%s", sep, mem_attrib[i]);
336 p += sprintf(p, "\n");
339 if ((status = ia64_pal_vm_page_size(&tr_pages, &vw_pages)) !=0) {
340 printk(KERN_ERR "ia64_pal_vm_page_size=%ld\n", status);
344 "\nTLB walker : %simplemented\n"
345 "Number of DTR : %d\n"
346 "Number of ITR : %d\n"
347 "TLB insertable page sizes : ",
348 vm_info_1.pal_vm_info_1_s.vw ? "" : "not ",
349 vm_info_1.pal_vm_info_1_s.max_dtr_entry+1,
350 vm_info_1.pal_vm_info_1_s.max_itr_entry+1);
353 p = bitvector_process(p, tr_pages);
355 p += sprintf(p, "\nTLB purgeable page sizes : ");
357 p = bitvector_process(p, vw_pages);
359 if ((status=ia64_get_ptce(&ptce)) != 0) {
360 printk(KERN_ERR "ia64_get_ptce=%ld\n", status);
363 "\nPurge base address : 0x%016lx\n"
364 "Purge outer loop count : %d\n"
365 "Purge inner loop count : %d\n"
366 "Purge outer loop stride : %d\n"
367 "Purge inner loop stride : %d\n",
368 ptce.base, ptce.count[0], ptce.count[1],
369 ptce.stride[0], ptce.stride[1]);
373 "Unique TC(s) : %d\n",
374 vm_info_1.pal_vm_info_1_s.num_tc_levels,
375 vm_info_1.pal_vm_info_1_s.max_unique_tcs);
377 for(i=0; i < vm_info_1.pal_vm_info_1_s.num_tc_levels; i++) {
378 for (j=2; j>0 ; j--) {
379 tc_pages = 0; /* just in case */
382 /* even without unification, some levels may not be present */
383 if ((status=ia64_pal_vm_info(i,j, &tc_info, &tc_pages)) != 0) {
388 "\n%s Translation Cache Level %d:\n"
390 "\tAssociativity : %d\n"
391 "\tNumber of entries : %d\n"
393 cache_types[j+tc_info.tc_unified], i+1,
395 tc_info.tc_associativity,
396 tc_info.tc_num_entries);
399 p += sprintf(p, "PreferredPageSizeOptimized ");
400 if (tc_info.tc_unified)
401 p += sprintf(p, "Unified ");
402 if (tc_info.tc_reduce_tr)
403 p += sprintf(p, "TCReduction");
405 p += sprintf(p, "\n\tSupported page sizes: ");
407 p = bitvector_process(p, tc_pages);
409 /* when unified date (j=2) is enough */
410 if (tc_info.tc_unified)
415 p += sprintf(p, "\n");
422 register_info(char *page)
432 "AR(s) with read side-effects",
434 "CR(s) with read side-effects",
437 for(info=0; info < 4; info++) {
439 if (ia64_pal_register_info(info, ®_info[0], ®_info[1]) != 0) return 0;
441 p += sprintf(p, "%-32s : ", info_type[info]);
443 p = bitregister_process(p, reg_info, 128);
445 p += sprintf(p, "\n");
448 if (ia64_pal_rse_info(&phys_stacked, &hints) == 0) {
451 "RSE stacked physical registers : %ld\n"
452 "RSE load/store hints : %ld (%s)\n",
453 phys_stacked, hints.ph_data,
454 hints.ph_data < RSE_HINTS_COUNT ? rse_hints[hints.ph_data]: "(??)");
456 if (ia64_pal_debug_info(&iregs, &dregs))
460 "Instruction debug register pairs : %ld\n"
461 "Data debug register pairs : %ld\n", iregs, dregs);
466 static const char *proc_features[]={
467 NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
468 NULL,NULL,NULL,NULL,NULL,NULL,NULL, NULL,NULL,
469 NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
470 NULL,NULL,NULL,NULL,NULL, NULL,NULL,NULL,NULL,
471 "Unimplemented instruction address fault",
472 "INIT, PMI, and LINT pins",
473 "Simple unimplemented instr addresses",
474 "Variable P-state performance",
475 "Virtual machine features implemented",
476 "XIP,XPSR,XFS implemented",
477 "XR1-XR3 implemented",
478 "Disable dynamic predicate prediction",
479 "Disable processor physical number",
480 "Disable dynamic data cache prefetch",
481 "Disable dynamic inst cache prefetch",
482 "Disable dynamic branch prediction",
483 NULL, NULL, NULL, NULL,
485 "Enable MCA on Data Poisoning",
486 "Enable vmsw instruction",
487 "Enable extern environmental notification",
488 "Disable BINIT on processor time-out",
489 "Disable dynamic power management (DPM)",
492 "Enable CMCI promotion",
493 "Enable MCA to BINIT promotion",
494 "Enable MCA promotion",
495 "Enable BERR promotion"
500 processor_info(char *page)
503 const char **v = proc_features;
504 u64 avail=1, status=1, control=1;
508 if ((ret=ia64_pal_proc_get_features(&avail, &status, &control)) != 0) return 0;
510 for(i=0; i < 64; i++, v++,avail >>=1, status >>=1, control >>=1) {
511 if ( ! *v ) continue;
512 p += sprintf(p, "%-40s : %s%s %s\n", *v,
513 avail & 0x1 ? "" : "NotImpl",
514 avail & 0x1 ? (status & 0x1 ? "On" : "Off"): "",
515 avail & 0x1 ? (control & 0x1 ? "Ctrl" : "NoCtrl"): "");
520 static const char *bus_features[]={
521 NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
522 NULL,NULL,NULL,NULL,NULL,NULL,NULL, NULL,NULL,
523 NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
525 "Request Bus Parking",
527 "Enable Half Transfer",
528 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
529 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
530 NULL, NULL, NULL, NULL,
531 "Enable Cache Line Repl. Shared",
532 "Enable Cache Line Repl. Exclusive",
533 "Disable Transaction Queuing",
534 "Disable Response Error Checking",
535 "Disable Bus Error Checking",
536 "Disable Bus Requester Internal Error Signalling",
537 "Disable Bus Requester Error Signalling",
538 "Disable Bus Initialization Event Checking",
539 "Disable Bus Initialization Event Signalling",
540 "Disable Bus Address Error Checking",
541 "Disable Bus Address Error Signalling",
542 "Disable Bus Data Error Checking"
550 const char **v = bus_features;
551 pal_bus_features_u_t av, st, ct;
552 u64 avail, status, control;
556 if ((ret=ia64_pal_bus_get_features(&av, &st, &ct)) != 0) return 0;
558 avail = av.pal_bus_features_val;
559 status = st.pal_bus_features_val;
560 control = ct.pal_bus_features_val;
562 for(i=0; i < 64; i++, v++, avail >>=1, status >>=1, control >>=1) {
563 if ( ! *v ) continue;
564 p += sprintf(p, "%-48s : %s%s %s\n", *v,
565 avail & 0x1 ? "" : "NotImpl",
566 avail & 0x1 ? (status & 0x1 ? "On" : "Off"): "",
567 avail & 0x1 ? (control & 0x1 ? "Ctrl" : "NoCtrl"): "");
573 version_info(char *page)
575 pal_version_u_t min_ver, cur_ver;
578 if (ia64_pal_version(&min_ver, &cur_ver) != 0)
582 "PAL_vendor : 0x%02x (min=0x%02x)\n"
583 "PAL_A : %02x.%02x (min=%02x.%02x)\n"
584 "PAL_B : %02x.%02x (min=%02x.%02x)\n",
585 cur_ver.pal_version_s.pv_pal_vendor,
586 min_ver.pal_version_s.pv_pal_vendor,
587 cur_ver.pal_version_s.pv_pal_a_model,
588 cur_ver.pal_version_s.pv_pal_a_rev,
589 min_ver.pal_version_s.pv_pal_a_model,
590 min_ver.pal_version_s.pv_pal_a_rev,
591 cur_ver.pal_version_s.pv_pal_b_model,
592 cur_ver.pal_version_s.pv_pal_b_rev,
593 min_ver.pal_version_s.pv_pal_b_model,
594 min_ver.pal_version_s.pv_pal_b_rev);
599 perfmon_info(char *page)
603 pal_perf_mon_info_u_t pm_info;
605 if (ia64_pal_perf_mon_info(pm_buffer, &pm_info) != 0) return 0;
608 "PMC/PMD pairs : %d\n"
609 "Counter width : %d bits\n"
610 "Cycle event number : %d\n"
611 "Retired event number : %d\n"
612 "Implemented PMC : ",
613 pm_info.pal_perf_mon_info_s.generic, pm_info.pal_perf_mon_info_s.width,
614 pm_info.pal_perf_mon_info_s.cycles, pm_info.pal_perf_mon_info_s.retired);
616 p = bitregister_process(p, pm_buffer, 256);
617 p += sprintf(p, "\nImplemented PMD : ");
618 p = bitregister_process(p, pm_buffer+4, 256);
619 p += sprintf(p, "\nCycles count capable : ");
620 p = bitregister_process(p, pm_buffer+8, 256);
621 p += sprintf(p, "\nRetired bundles count capable : ");
623 #ifdef CONFIG_ITANIUM
625 * PAL_PERF_MON_INFO reports that only PMC4 can be used to count CPU_CYCLES
626 * which is wrong, both PMC4 and PMD5 support it.
628 if (pm_buffer[12] == 0x10) pm_buffer[12]=0x30;
631 p = bitregister_process(p, pm_buffer+12, 256);
633 p += sprintf(p, "\n");
639 frequency_info(char *page)
642 struct pal_freq_ratio proc, itc, bus;
645 if (ia64_pal_freq_base(&base) == -1)
646 p += sprintf(p, "Output clock : not implemented\n");
648 p += sprintf(p, "Output clock : %ld ticks/s\n", base);
650 if (ia64_pal_freq_ratios(&proc, &bus, &itc) != 0) return 0;
653 "Processor/Clock ratio : %d/%d\n"
654 "Bus/Clock ratio : %d/%d\n"
655 "ITC/Clock ratio : %d/%d\n",
656 proc.num, proc.den, bus.num, bus.den, itc.num, itc.den);
666 pal_tr_valid_u_t tr_valid;
668 pal_vm_info_1_u_t vm_info_1;
669 pal_vm_info_2_u_t vm_info_2;
704 if ((status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2)) !=0) {
705 printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
708 max[0] = vm_info_1.pal_vm_info_1_s.max_itr_entry+1;
709 max[1] = vm_info_1.pal_vm_info_1_s.max_dtr_entry+1;
711 for (i=0; i < 2; i++ ) {
712 for (j=0; j < max[i]; j++) {
714 status = ia64_pal_tr_read(j, i, tr_buffer, &tr_valid);
716 printk(KERN_ERR "palinfo: pal call failed on tr[%lu:%lu]=%ld\n",
721 ifa_reg = (struct ifa_reg *)&tr_buffer[2];
723 if (ifa_reg->valid == 0) continue;
725 gr_reg = (struct gr_reg *)tr_buffer;
726 itir_reg = (struct itir_reg *)&tr_buffer[1];
727 rid_reg = (struct rid_reg *)&tr_buffer[3];
729 pgm = -1 << (itir_reg->ps - 12);
731 "%cTR%lu: av=%d pv=%d dv=%d mv=%d\n"
736 tr_valid.pal_tr_valid_s.access_rights_valid,
737 tr_valid.pal_tr_valid_s.priv_level_valid,
738 tr_valid.pal_tr_valid_s.dirty_bit_valid,
739 tr_valid.pal_tr_valid_s.mem_attr_valid,
740 (gr_reg->ppn & pgm)<< 12, (ifa_reg->vpn & pgm)<< 12);
742 p = bitvector_process(p, 1<< itir_reg->ps);
751 gr_reg->pl, gr_reg->ar, rid_reg->rid, gr_reg->p, gr_reg->ma,
761 * List {name,function} pairs for every entry in /proc/palinfo/cpu*
763 static palinfo_entry_t palinfo_entries[]={
764 { "version_info", version_info, },
765 { "vm_info", vm_info, },
766 { "cache_info", cache_info, },
767 { "power_info", power_info, },
768 { "register_info", register_info, },
769 { "processor_info", processor_info, },
770 { "perfmon_info", perfmon_info, },
771 { "frequency_info", frequency_info, },
772 { "bus_info", bus_info },
773 { "tr_info", tr_info, }
776 #define NR_PALINFO_ENTRIES (int) ARRAY_SIZE(palinfo_entries)
779 * this array is used to keep track of the proc entries we create. This is
780 * required in the module mode when we need to remove all entries. The procfs code
781 * does not do recursion of deletion
784 * - +1 accounts for the cpuN directory entry in /proc/pal
786 #define NR_PALINFO_PROC_ENTRIES (NR_CPUS*(NR_PALINFO_ENTRIES+1))
788 static struct proc_dir_entry *palinfo_proc_entries[NR_PALINFO_PROC_ENTRIES];
789 static struct proc_dir_entry *palinfo_dir;
792 * This data structure is used to pass which cpu,function is being requested
793 * It must fit in a 64bit quantity to be passed to the proc callback routine
795 * In SMP mode, when we get a request for another CPU, we must call that
796 * other CPU using IPI and wait for the result before returning.
801 unsigned req_cpu: 32; /* for which CPU this info is */
802 unsigned func_id: 32; /* which function is requested */
806 #define req_cpu pal_func_cpu.req_cpu
807 #define func_id pal_func_cpu.func_id
812 * used to hold information about final function to call
815 palinfo_func_t func; /* pointer to function to call */
816 char *page; /* buffer to store results */
817 int ret; /* return value from call */
818 } palinfo_smp_data_t;
822 * this function does the actual final call and he called
823 * from the smp code, i.e., this is the palinfo callback routine
826 palinfo_smp_call(void *info)
828 palinfo_smp_data_t *data = (palinfo_smp_data_t *)info;
830 printk(KERN_ERR "palinfo: data pointer is NULL\n");
831 data->ret = 0; /* no output */
834 /* does this actual call */
835 data->ret = (*data->func)(data->page);
839 * function called to trigger the IPI, we need to access a remote CPU
841 * 0 : error or nothing to output
842 * otherwise how many bytes in the "page" buffer were written
845 int palinfo_handle_smp(pal_func_cpu_u_t *f, char *page)
847 palinfo_smp_data_t ptr;
850 ptr.func = palinfo_entries[f->func_id].proc_read;
852 ptr.ret = 0; /* just in case */
855 /* will send IPI to other CPU and wait for completion of remote call */
856 if ((ret=smp_call_function_single(f->req_cpu, palinfo_smp_call, &ptr, 0, 1))) {
857 printk(KERN_ERR "palinfo: remote CPU call from %d to %d on function %d: "
858 "error %d\n", smp_processor_id(), f->req_cpu, f->func_id, ret);
863 #else /* ! CONFIG_SMP */
865 int palinfo_handle_smp(pal_func_cpu_u_t *f, char *page)
867 printk(KERN_ERR "palinfo: should not be called with non SMP kernel\n");
870 #endif /* CONFIG_SMP */
873 * Entry point routine: all calls go through this function
876 palinfo_read_entry(char *page, char **start, off_t off, int count, int *eof, void *data)
879 pal_func_cpu_u_t *f = (pal_func_cpu_u_t *)&data;
882 * in SMP mode, we may need to call another CPU to get correct
883 * information. PAL, by definition, is processor specific
885 if (f->req_cpu == get_cpu())
886 len = (*palinfo_entries[f->func_id].proc_read)(page);
888 len = palinfo_handle_smp(f, page);
892 if (len <= off+count) *eof = 1;
897 if (len>count) len = count;
904 create_palinfo_proc_entries(unsigned int cpu)
906 # define CPUSTR "cpu%d"
909 struct proc_dir_entry **pdir;
910 struct proc_dir_entry *cpu_dir;
912 char cpustr[sizeof(CPUSTR)];
916 * we keep track of created entries in a depth-first order for
917 * cleanup purposes. Each entry is stored into palinfo_proc_entries
919 sprintf(cpustr,CPUSTR, cpu);
921 cpu_dir = proc_mkdir(cpustr, palinfo_dir);
926 * Compute the location to store per cpu entries
927 * We dont store the top level entry in this list, but
928 * remove it finally after removing all cpu entries.
930 pdir = &palinfo_proc_entries[cpu*(NR_PALINFO_ENTRIES+1)];
932 for (j=0; j < NR_PALINFO_ENTRIES; j++) {
934 *pdir = create_proc_read_entry(
935 palinfo_entries[j].name, 0, cpu_dir,
936 palinfo_read_entry, (void *)f.value);
938 (*pdir)->owner = THIS_MODULE;
944 remove_palinfo_proc_entries(unsigned int hcpu)
947 struct proc_dir_entry *cpu_dir, **pdir;
949 pdir = &palinfo_proc_entries[hcpu*(NR_PALINFO_ENTRIES+1)];
952 for (j=0; j < (NR_PALINFO_ENTRIES); j++) {
954 remove_proc_entry ((*pdir)->name, cpu_dir);
960 remove_proc_entry(cpu_dir->name, palinfo_dir);
964 #ifdef CONFIG_HOTPLUG_CPU
965 static int palinfo_cpu_callback(struct notifier_block *nfb,
966 unsigned long action, void *hcpu)
968 unsigned int hotcpu = (unsigned long)hcpu;
972 create_palinfo_proc_entries(hotcpu);
975 remove_palinfo_proc_entries(hotcpu);
981 static struct notifier_block palinfo_cpu_notifier =
983 .notifier_call = palinfo_cpu_callback,
993 printk(KERN_INFO "PAL Information Facility v%s\n", PALINFO_VERSION);
994 palinfo_dir = proc_mkdir("pal", NULL);
996 /* Create palinfo dirs in /proc for all online cpus */
997 for_each_online_cpu(i) {
998 create_palinfo_proc_entries(i);
1001 /* Register for future delivery via notify registration */
1002 register_hotcpu_notifier(&palinfo_cpu_notifier);
1012 /* remove all nodes: depth first pass. Could optimize this */
1013 for_each_online_cpu(i) {
1014 remove_palinfo_proc_entries(i);
1018 * Remove the top level entry finally
1020 remove_proc_entry(palinfo_dir->name, NULL);
1023 * Unregister from cpu notifier callbacks
1025 unregister_hotcpu_notifier(&palinfo_cpu_notifier);
1028 module_init(palinfo_init);
1029 module_exit(palinfo_exit);