2 * arch/ia64/kernel/ivt.S
4 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger <davidm@hpl.hp.com>
7 * Copyright (C) 2000, 2002-2003 Intel Co
8 * Asit Mallick <asit.k.mallick@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Kenneth Chen <kenneth.w.chen@intel.com>
11 * Fenghua Yu <fenghua.yu@intel.com>
13 * 00/08/23 Asit Mallick <asit.k.mallick@intel.com> TLB handling for SMP
14 * 00/12/20 David Mosberger-Tang <davidm@hpl.hp.com> DTLB/ITLB handler now uses virtual PT.
17 * This file defines the interruption vector table used by the CPU.
18 * It does not include one entry per possible cause of interruption.
20 * The first 20 entries of the table contain 64 bundles each while the
21 * remaining 48 entries contain only 16 bundles each.
23 * The 64 bundles are used to allow inlining the whole handler for critical
24 * interruptions like TLB misses.
26 * For each entry, the comment is as follows:
28 * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
29 * entry offset ----/ / / / /
30 * entry number ---------/ / / /
31 * size of the entry -------------/ / /
32 * vector name -------------------------------------/ /
33 * interruptions triggering this vector ----------------------/
35 * The table is 32KB in size and must be aligned on 32KB boundary.
36 * (The CPU ignores the 15 lower bits of the address)
38 * Table is based upon EAS2.6 (Oct 1999)
41 #include <linux/config.h>
43 #include <asm/asmmacro.h>
44 #include <asm/break.h>
46 #include <asm/kregs.h>
47 #include <asm/asm-offsets.h>
48 #include <asm/pgtable.h>
49 #include <asm/processor.h>
50 #include <asm/ptrace.h>
51 #include <asm/system.h>
52 #include <asm/thread_info.h>
53 #include <asm/unistd.h>
54 #include <asm/errno.h>
57 # define PSR_DEFAULT_BITS psr.ac
59 # define PSR_DEFAULT_BITS 0
64 * This lets you track the last eight faults that occurred on the CPU. Make sure ar.k2 isn't
65 * needed for something else before enabling this...
67 # define DBG_FAULT(i) mov r16=ar.k2;; shl r16=r16,8;; add r16=(i),r16;;mov ar.k2=r16
76 mov r19=n;; /* prepare to save predicates */ \
77 br.sptk.many dispatch_to_fault_handler
79 .section .text.ivt,"ax"
81 .align 32768 // align on 32KB boundary
84 /////////////////////////////////////////////////////////////////////////////////////////
85 // 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
89 * The VHPT vector is invoked when the TLB entry for the virtual page table
90 * is missing. This happens only as a result of a previous
91 * (the "original") TLB miss, which may either be caused by an instruction
92 * fetch or a data access (or non-access).
94 * What we do here is normal TLB miss handing for the _original_ miss, followed
95 * by inserting the TLB entry for the virtual page table page that the VHPT
96 * walker was attempting to access. The latter gets inserted as long
97 * as both L1 and L2 have valid mappings for the faulting address.
98 * The TLB entry for the original miss gets inserted only if
99 * the L3 entry indicates that the page is present.
101 * do_page_fault gets invoked in the following cases:
102 * - the faulting virtual address uses unimplemented address bits
103 * - the faulting virtual address has no L1, L2, or L3 mapping
105 mov r16=cr.ifa // get address that caused the TLB miss
106 #ifdef CONFIG_HUGETLB_PAGE
111 rsm psr.dt // use physical addressing for data
112 mov r31=pr // save the predicate registers
113 mov r19=IA64_KR(PT_BASE) // get page table base address
114 shl r21=r16,3 // shift bit 60 into sign bit
115 shr.u r17=r16,61 // get the region number into r17
118 #ifdef CONFIG_HUGETLB_PAGE
124 (p8) dep r25=r18,r25,2,6
128 cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5?
129 shr.u r18=r22,PGDIR_SHIFT // get bits 33-63 of the faulting address
131 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
134 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
136 .pred.rel "mutex", p6, p7
137 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
138 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
140 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
141 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
142 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
143 #ifdef CONFIG_PGTABLE_4
144 shr.u r28=r22,PUD_SHIFT // shift L2 index into position
146 shr.u r18=r22,PMD_SHIFT // shift L3 index into position
149 ld8 r17=[r17] // fetch the L1 entry (may be 0)
151 (p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
152 #ifdef CONFIG_PGTABLE_4
153 dep r28=r28,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
155 shr.u r18=r22,PMD_SHIFT // shift L3 index into position
156 (p7) ld8 r29=[r28] // fetch the L2 entry (may be 0)
158 (p7) cmp.eq.or.andcm p6,p7=r29,r0 // was L2 entry NULL?
159 dep r17=r18,r29,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
161 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
164 (p7) ld8 r20=[r17] // fetch the L3 entry (may be 0)
165 shr.u r19=r22,PAGE_SHIFT // shift L4 index into position
167 (p7) cmp.eq.or.andcm p6,p7=r20,r0 // was L3 entry NULL?
168 dep r21=r19,r20,3,(PAGE_SHIFT-3) // compute address of L4 page table entry
170 (p7) ld8 r18=[r21] // read the L4 PTE
171 mov r19=cr.isr // cr.isr bit 0 tells us if this is an insn miss
173 (p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared?
174 mov r22=cr.iha // get the VHPT address that caused the TLB miss
175 ;; // avoid RAW on p7
176 (p7) tbit.nz.unc p10,p11=r19,32 // is it an instruction TLB miss?
177 dep r23=0,r20,0,PAGE_SHIFT // clear low bits to get page address
179 (p10) itc.i r18 // insert the instruction TLB entry
180 (p11) itc.d r18 // insert the data TLB entry
181 (p6) br.cond.spnt.many page_fault // handle bad address/page not present (page fault)
184 #ifdef CONFIG_HUGETLB_PAGE
185 (p8) mov cr.itir=r25 // change to default page-size for VHPT
189 * Now compute and insert the TLB entry for the virtual page table. We never
190 * execute in a page table page so there is no need to set the exception deferral
193 adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23
199 * Tell the assemblers dependency-violation checker that the above "itc" instructions
200 * cannot possibly affect the following loads:
205 * Re-check L2 and L3 pagetable. If they changed, we may have received a ptc.g
206 * between reading the pagetable and the "itc". If so, flush the entry we
207 * inserted and retry.
209 ld8 r25=[r21] // read L4 entry again
210 ld8 r26=[r17] // read L3 PTE again
211 #ifdef CONFIG_PGTABLE_4
212 ld8 r18=[r28] // read L2 entry again
216 cmp.ne.or.andcm p6,p7=r26,r20 // did L3 entry change
217 #ifdef CONFIG_PGTABLE_4
218 cmp.ne.or.andcm p6,p7=r29,r18 // did L4 PTE change
220 mov r27=PAGE_SHIFT<<2
222 (p6) ptc.l r22,r27 // purge PTE page translation
223 (p7) cmp.ne.or.andcm p6,p7=r25,r18 // did L4 PTE change
225 (p6) ptc.l r16,r27 // purge translation
228 mov pr=r31,-1 // restore predicate registers
233 /////////////////////////////////////////////////////////////////////////////////////////
234 // 0x0400 Entry 1 (size 64 bundles) ITLB (21)
238 * The ITLB handler accesses the L3 PTE via the virtually mapped linear
239 * page table. If a nested TLB miss occurs, we switch into physical
240 * mode, walk the page table, and then re-execute the L3 PTE read
241 * and go on normally after that.
243 mov r16=cr.ifa // get virtual address
244 mov r29=b0 // save b0
245 mov r31=pr // save predicates
247 mov r17=cr.iha // get virtual address of L3 PTE
248 movl r30=1f // load nested fault continuation point
250 1: ld8 r18=[r17] // read L3 PTE
253 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
254 (p6) br.cond.spnt page_fault
260 * Tell the assemblers dependency-violation checker that the above "itc" instructions
261 * cannot possibly affect the following loads:
265 ld8 r19=[r17] // read L3 PTE again and see if same
266 mov r20=PAGE_SHIFT<<2 // setup page size for purge
277 /////////////////////////////////////////////////////////////////////////////////////////
278 // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
282 * The DTLB handler accesses the L3 PTE via the virtually mapped linear
283 * page table. If a nested TLB miss occurs, we switch into physical
284 * mode, walk the page table, and then re-execute the L3 PTE read
285 * and go on normally after that.
287 mov r16=cr.ifa // get virtual address
288 mov r29=b0 // save b0
289 mov r31=pr // save predicates
291 mov r17=cr.iha // get virtual address of L3 PTE
292 movl r30=1f // load nested fault continuation point
294 1: ld8 r18=[r17] // read L3 PTE
297 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
298 (p6) br.cond.spnt page_fault
304 * Tell the assemblers dependency-violation checker that the above "itc" instructions
305 * cannot possibly affect the following loads:
309 ld8 r19=[r17] // read L3 PTE again and see if same
310 mov r20=PAGE_SHIFT<<2 // setup page size for purge
321 /////////////////////////////////////////////////////////////////////////////////////////
322 // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
325 mov r16=cr.ifa // get address that caused the TLB miss
328 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
331 #ifdef CONFIG_DISABLE_VHPT
332 shr.u r22=r16,61 // get the region number into r21
334 cmp.gt p8,p0=6,r22 // user mode
339 (p8) mov r29=b0 // save b0
340 (p8) br.cond.dptk .itlb_fault
342 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
343 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
344 shr.u r18=r16,57 // move address bit 61 to bit 4
346 andcm r18=0x10,r18 // bit 4=~address-bit(61)
347 cmp.ne p8,p0=r0,r23 // psr.cpl != 0?
348 or r19=r17,r19 // insert PTE control bits into r19
350 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
351 (p8) br.cond.spnt page_fault
353 itc.i r19 // insert the TLB entry
359 /////////////////////////////////////////////////////////////////////////////////////////
360 // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
363 mov r16=cr.ifa // get address that caused the TLB miss
366 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
370 #ifdef CONFIG_DISABLE_VHPT
371 shr.u r22=r16,61 // get the region number into r21
373 cmp.gt p8,p0=6,r22 // access to region 0-5
378 (p8) mov r29=b0 // save b0
379 (p8) br.cond.dptk dtlb_fault
381 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
382 and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field
383 tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on?
384 shr.u r18=r16,57 // move address bit 61 to bit 4
385 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
386 tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on?
388 andcm r18=0x10,r18 // bit 4=~address-bit(61)
390 (p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field
391 (p8) br.cond.spnt page_fault
393 dep r21=-1,r21,IA64_PSR_ED_BIT,1
394 or r19=r19,r17 // insert PTE control bits into r19
396 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
399 (p7) itc.d r19 // insert the TLB entry
405 /////////////////////////////////////////////////////////////////////////////////////////
406 // 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
407 ENTRY(nested_dtlb_miss)
409 * In the absence of kernel bugs, we get here when the virtually mapped linear
410 * page table is accessed non-speculatively (e.g., in the Dirty-bit, Instruction
411 * Access-bit, or Data Access-bit faults). If the DTLB entry for the virtual page
412 * table is missing, a nested TLB miss fault is triggered and control is
413 * transferred to this point. When this happens, we lookup the pte for the
414 * faulting address by walking the page table in physical mode and return to the
415 * continuation point passed in register r30 (or call page_fault if the address is
418 * Input: r16: faulting address
420 * r30: continuation address
423 * Output: r17: physical address of L3 PTE of faulting address
425 * r30: continuation address
428 * Clobbered: b0, r18, r19, r21, r22, psr.dt (cleared)
430 rsm psr.dt // switch to using physical data addressing
431 mov r19=IA64_KR(PT_BASE) // get the page table base address
432 shl r21=r16,3 // shift bit 60 into sign bit
435 shr.u r17=r16,61 // get the region number into r17
436 extr.u r18=r18,2,6 // get the faulting page size
438 cmp.eq p6,p7=5,r17 // is faulting address in region 5?
439 add r22=-PAGE_SHIFT,r18 // adjustment for hugetlb address
440 add r18=PGDIR_SHIFT-PAGE_SHIFT,r18
444 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
447 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
449 .pred.rel "mutex", p6, p7
450 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
451 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
453 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
454 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
455 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
456 #ifdef CONFIG_PGTABLE_4
457 shr.u r18=r22,PUD_SHIFT // shift L2 index into position
459 shr.u r18=r22,PMD_SHIFT // shift L3 index into position
462 ld8 r17=[r17] // fetch the L1 entry (may be 0)
464 (p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
465 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
467 #ifdef CONFIG_PGTABLE_4
468 (p7) ld8 r17=[r17] // fetch the L2 entry (may be 0)
469 shr.u r18=r22,PMD_SHIFT // shift L3 index into position
471 (p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L2 entry NULL?
472 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
475 (p7) ld8 r17=[r17] // fetch the L3 entry (may be 0)
476 shr.u r19=r22,PAGE_SHIFT // shift L4 index into position
478 (p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L3 entry NULL?
479 dep r17=r19,r17,3,(PAGE_SHIFT-3) // compute address of L4 page table entry
480 (p6) br.cond.spnt page_fault
482 br.sptk.many b0 // return to continuation point
483 END(nested_dtlb_miss)
486 /////////////////////////////////////////////////////////////////////////////////////////
487 // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
493 //-----------------------------------------------------------------------------------
494 // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address)
501 alloc r15=ar.pfs,0,0,3,0
504 adds r3=8,r2 // set up second base pointer
506 ssm psr.ic | PSR_DEFAULT_BITS
508 srlz.i // guarantee that interruption collectin is on
510 (p15) ssm psr.i // restore psr.i
511 movl r14=ia64_leave_kernel
516 adds out2=16,r12 // out2 = pointer to pt_regs
517 br.call.sptk.many b6=ia64_do_page_fault // ignore return address
521 /////////////////////////////////////////////////////////////////////////////////////////
522 // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
529 /////////////////////////////////////////////////////////////////////////////////////////
530 // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
534 * What we do here is to simply turn on the dirty bit in the PTE. We need to
535 * update both the page-table and the TLB entry. To efficiently access the PTE,
536 * we address it through the virtual page table. Most likely, the TLB entry for
537 * the relevant virtual page table page is still present in the TLB so we can
538 * normally do this without additional TLB misses. In case the necessary virtual
539 * page table TLB entry isn't present, we take a nested TLB miss hit where we look
540 * up the physical address of the L3 PTE and then continue at label 1 below.
542 mov r16=cr.ifa // get the address that caused the fault
543 movl r30=1f // load continuation point in case of nested fault
545 thash r17=r16 // compute virtual address of L3 PTE
546 mov r29=b0 // save b0 in case of nested fault
547 mov r31=pr // save pr
549 mov r28=ar.ccv // save ar.ccv
552 ;; // avoid RAW on r18
553 mov ar.ccv=r18 // set compare value for cmpxchg
554 or r25=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
556 cmpxchg8.acq r26=[r17],r25,ar.ccv
557 mov r24=PAGE_SHIFT<<2
561 (p6) itc.d r25 // install updated PTE
564 * Tell the assemblers dependency-violation checker that the above "itc" instructions
565 * cannot possibly affect the following loads:
569 ld8 r18=[r17] // read PTE again
571 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
574 mov b0=r29 // restore b0
579 ;; // avoid RAW on r18
580 or r18=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
581 mov b0=r29 // restore b0
583 st8 [r17]=r18 // store back updated PTE
584 itc.d r18 // install updated PTE
586 mov pr=r31,-1 // restore pr
591 /////////////////////////////////////////////////////////////////////////////////////////
592 // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
595 // Like Entry 8, except for instruction access
596 mov r16=cr.ifa // get the address that caused the fault
597 movl r30=1f // load continuation point in case of nested fault
598 mov r31=pr // save predicates
599 #ifdef CONFIG_ITANIUM
601 * Erratum 10 (IFA may contain incorrect address) has "NoFix" status.
606 tbit.z p6,p0=r17,IA64_PSR_IS_BIT // IA64 instruction set?
608 (p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa
609 #endif /* CONFIG_ITANIUM */
611 thash r17=r16 // compute virtual address of L3 PTE
612 mov r29=b0 // save b0 in case of nested fault)
614 mov r28=ar.ccv // save ar.ccv
618 mov ar.ccv=r18 // set compare value for cmpxchg
619 or r25=_PAGE_A,r18 // set the accessed bit
621 cmpxchg8.acq r26=[r17],r25,ar.ccv
622 mov r24=PAGE_SHIFT<<2
626 (p6) itc.i r25 // install updated PTE
629 * Tell the assemblers dependency-violation checker that the above "itc" instructions
630 * cannot possibly affect the following loads:
634 ld8 r18=[r17] // read PTE again
636 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
639 mov b0=r29 // restore b0
641 #else /* !CONFIG_SMP */
645 or r18=_PAGE_A,r18 // set the accessed bit
646 mov b0=r29 // restore b0
648 st8 [r17]=r18 // store back updated PTE
649 itc.i r18 // install updated PTE
650 #endif /* !CONFIG_SMP */
656 /////////////////////////////////////////////////////////////////////////////////////////
657 // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
660 // Like Entry 8, except for data access
661 mov r16=cr.ifa // get the address that caused the fault
662 movl r30=1f // load continuation point in case of nested fault
664 thash r17=r16 // compute virtual address of L3 PTE
666 mov r29=b0 // save b0 in case of nested fault)
668 mov r28=ar.ccv // save ar.ccv
671 ;; // avoid RAW on r18
672 mov ar.ccv=r18 // set compare value for cmpxchg
673 or r25=_PAGE_A,r18 // set the dirty bit
675 cmpxchg8.acq r26=[r17],r25,ar.ccv
676 mov r24=PAGE_SHIFT<<2
680 (p6) itc.d r25 // install updated PTE
682 * Tell the assemblers dependency-violation checker that the above "itc" instructions
683 * cannot possibly affect the following loads:
687 ld8 r18=[r17] // read PTE again
689 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
696 ;; // avoid RAW on r18
697 or r18=_PAGE_A,r18 // set the accessed bit
699 st8 [r17]=r18 // store back updated PTE
700 itc.d r18 // install updated PTE
702 mov b0=r29 // restore b0
708 /////////////////////////////////////////////////////////////////////////////////////////
709 // 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
712 * The streamlined system call entry/exit paths only save/restore the initial part
713 * of pt_regs. This implies that the callers of system-calls must adhere to the
714 * normal procedure calling conventions.
716 * Registers to be saved & restored:
717 * CR registers: cr.ipsr, cr.iip, cr.ifs
718 * AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore, ar.fpsr
719 * others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15
720 * Registers to be restored only:
721 * r8-r11: output value from the system call.
723 * During system call exit, scratch registers (including r15) are modified/cleared
724 * to prevent leaking bits from kernel to user level.
727 mov.m r16=IA64_KR(CURRENT) // M2 r16 <- current task (12 cyc)
728 mov r29=cr.ipsr // M2 (12 cyc)
729 mov r31=pr // I0 (2 cyc)
731 mov r17=cr.iim // M2 (2 cyc)
732 mov.m r27=ar.rsc // M2 (12 cyc)
733 mov r18=__IA64_BREAK_SYSCALL // A
736 mov.m r21=ar.fpsr // M2 (12 cyc)
737 mov r19=b6 // I0 (2 cyc)
739 mov.m r23=ar.bspstore // M2 (12 cyc)
740 mov.m r24=ar.rnat // M2 (5 cyc)
741 mov.i r26=ar.pfs // I0 (2 cyc)
745 mov r20=r1 // A save r1
748 movl r30=sys_call_table // X
750 mov r28=cr.iip // M2 (2 cyc)
751 cmp.eq p0,p7=r18,r17 // I0 is this a system call?
752 (p7) br.cond.spnt non_syscall // B no ->
754 // From this point on, we are definitely on the syscall-path
755 // and we can use (non-banked) scratch registers.
757 ///////////////////////////////////////////////////////////////////////
758 mov r1=r16 // A move task-pointer to "addl"-addressable reg
759 mov r2=r16 // A setup r2 for ia64_syscall_setup
760 add r9=TI_FLAGS+IA64_TASK_SIZE,r16 // A r9 = ¤t_thread_info()->flags
762 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
763 adds r15=-1024,r15 // A subtract 1024 from syscall number
764 mov r3=NR_syscalls - 1
766 ld1.bias r17=[r16] // M0|1 r17 = current->thread.on_ustack flag
767 ld4 r9=[r9] // M0|1 r9 = current_thread_info()->flags
768 extr.u r8=r29,41,2 // I0 extract ei field from cr.ipsr
770 shladd r30=r15,3,r30 // A r30 = sys_call_table + 8*(syscall-1024)
771 addl r22=IA64_RBS_OFFSET,r1 // A compute base of RBS
772 cmp.leu p6,p7=r15,r3 // A syscall number in range?
775 lfetch.fault.excl.nt1 [r22] // M0|1 prefetch RBS
776 (p6) ld8 r30=[r30] // M0|1 load address of syscall entry point
777 tnat.nz.or p7,p0=r15 // I0 is syscall nr a NaT?
779 mov.m ar.bspstore=r22 // M2 switch to kernel RBS
780 cmp.eq p8,p9=2,r8 // A isr.ei==2?
783 (p8) mov r8=0 // A clear ei to 0
784 (p7) movl r30=sys_ni_syscall // X
786 (p8) adds r28=16,r28 // A switch cr.iip to next bundle
787 (p9) adds r8=1,r8 // A increment ei to next slot
791 mov.m r25=ar.unat // M2 (5 cyc)
792 dep r29=r8,r29,41,2 // I0 insert new ei into cr.ipsr
793 adds r15=1024,r15 // A restore original syscall number
795 // If any of the above loads miss in L1D, we'll stall here until
798 ///////////////////////////////////////////////////////////////////////
799 st1 [r16]=r0 // M2|3 clear current->thread.on_ustack flag
800 mov b6=r30 // I0 setup syscall handler branch reg early
801 cmp.eq pKStk,pUStk=r0,r17 // A were we on kernel stacks already?
803 and r9=_TIF_SYSCALL_TRACEAUDIT,r9 // A mask trace or audit
804 mov r18=ar.bsp // M2 (12 cyc)
805 (pKStk) br.cond.spnt .break_fixup // B we're already in kernel-mode -- fix up RBS
807 .back_from_break_fixup:
808 (pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1 // A compute base of memory stack
809 cmp.eq p14,p0=r9,r0 // A are syscalls being traced/audited?
810 br.call.sptk.many b7=ia64_syscall_setup // B
812 mov ar.rsc=0x3 // M2 set eager mode, pl 0, LE, loadrs=0
814 bsw.1 // B (6 cyc) regs are saved, switch to bank 1
817 ssm psr.ic | PSR_DEFAULT_BITS // M2 now it's safe to re-enable intr.-collection
818 movl r3=ia64_ret_from_syscall // X
821 srlz.i // M0 ensure interruption collection is on
822 mov rp=r3 // I0 set the real return addr
823 (p10) br.cond.spnt.many ia64_ret_from_syscall // B return if bad call-frame or r15 is a NaT
825 (p15) ssm psr.i // M2 restore psr.i
826 (p14) br.call.sptk.many b6=b6 // B invoke syscall-handker (ignore return addr)
827 br.cond.spnt.many ia64_trace_syscall // B do syscall-tracing thingamagic
829 ///////////////////////////////////////////////////////////////////////
830 // On entry, we optimistically assumed that we're coming from user-space.
831 // For the rare cases where a system-call is done from within the kernel,
832 // we fix things up at this point:
834 add r1=-IA64_PT_REGS_SIZE,sp // A allocate space for pt_regs structure
835 mov ar.rnat=r24 // M2 restore kernel's AR.RNAT
837 mov ar.bspstore=r23 // M2 restore kernel's AR.BSPSTORE
838 br.cond.sptk .back_from_break_fixup
842 /////////////////////////////////////////////////////////////////////////////////////////
843 // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
846 mov r31=pr // prepare to save predicates
848 SAVE_MIN_WITH_COVER // uses r31; defines r2 and r3
849 ssm psr.ic | PSR_DEFAULT_BITS
851 adds r3=8,r2 // set up second base pointer for SAVE_REST
852 srlz.i // ensure everybody knows psr.ic is back on
856 alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
857 mov out0=cr.ivr // pass cr.ivr as first arg
858 add out1=16,sp // pass pointer to pt_regs as second arg
860 srlz.d // make sure we see the effect of cr.ivr
861 movl r14=ia64_leave_kernel
864 br.call.sptk.many b6=ia64_handle_irq
868 /////////////////////////////////////////////////////////////////////////////////////////
869 // 0x3400 Entry 13 (size 64 bundles) Reserved
874 /////////////////////////////////////////////////////////////////////////////////////////
875 // 0x3800 Entry 14 (size 64 bundles) Reserved
880 * There is no particular reason for this code to be here, other than that
881 * there happens to be space here that would go unused otherwise. If this
882 * fault ever gets "unreserved", simply moved the following code to a more
885 * ia64_syscall_setup() is a separate subroutine so that it can
886 * allocate stacked registers so it can safely demine any
887 * potential NaT values from the input registers.
890 * - executing on bank 0 or bank 1 register set (doesn't matter)
891 * - r1: stack pointer
892 * - r2: current task pointer
894 * - r11: original contents (saved ar.pfs to be saved)
895 * - r12: original contents (sp to be saved)
896 * - r13: original contents (tp to be saved)
897 * - r15: original contents (syscall # to be saved)
898 * - r18: saved bsp (after switching to kernel stack)
900 * - r20: saved r1 (gp)
901 * - r21: saved ar.fpsr
902 * - r22: kernel's register backing store base (krbs_base)
903 * - r23: saved ar.bspstore
904 * - r24: saved ar.rnat
905 * - r25: saved ar.unat
906 * - r26: saved ar.pfs
907 * - r27: saved ar.rsc
908 * - r28: saved cr.iip
909 * - r29: saved cr.ipsr
911 * - b0: original contents (to be saved)
913 * - p10: TRUE if syscall is invoked with more than 8 out
914 * registers or r15's Nat is true
916 * - r3: preserved (same as on entry)
917 * - r8: -EINVAL if p10 is true
918 * - r12: points to kernel stack
919 * - r13: points to current task
920 * - r14: preserved (same as on entry)
922 * - p15: TRUE if interrupts need to be re-enabled
923 * - ar.fpsr: set to kernel settings
924 * - b6: preserved (same as on entry)
926 GLOBAL_ENTRY(ia64_syscall_setup)
928 # error This code assumes that b6 is the first field in pt_regs.
930 st8 [r1]=r19 // save b6
931 add r16=PT(CR_IPSR),r1 // initialize first base pointer
932 add r17=PT(R11),r1 // initialize second base pointer
934 alloc r19=ar.pfs,8,0,0,0 // ensure in0-in7 are writable
935 st8 [r16]=r29,PT(AR_PFS)-PT(CR_IPSR) // save cr.ipsr
938 st8.spill [r17]=r11,PT(CR_IIP)-PT(R11) // save r11
940 (pKStk) mov r18=r0 // make sure r18 isn't NaT
943 st8 [r16]=r26,PT(CR_IFS)-PT(AR_PFS) // save ar.pfs
944 st8 [r17]=r28,PT(AR_UNAT)-PT(CR_IIP) // save cr.iip
945 mov r28=b0 // save b0 (2 cyc)
948 st8 [r17]=r25,PT(AR_RSC)-PT(AR_UNAT) // save ar.unat
949 dep r19=0,r19,38,26 // clear all bits but 0..37 [I0]
953 st8 [r16]=r19,PT(AR_RNAT)-PT(CR_IFS) // store ar.pfs.pfm in cr.ifs
954 extr.u r11=r19,7,7 // I0 // get sol of ar.pfs
955 and r8=0x7f,r19 // A // get sof of ar.pfs
957 st8 [r17]=r27,PT(AR_BSPSTORE)-PT(AR_RSC)// save ar.rsc
958 tbit.nz p15,p0=r29,IA64_PSR_I_BIT // I0
962 (pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8
966 (pKStk) adds r16=PT(PR)-PT(AR_RNAT),r16 // skip over ar_rnat field
967 (pKStk) adds r17=PT(B0)-PT(AR_BSPSTORE),r17 // skip over ar_bspstore field
971 tnat.nz p12,p0=in4 // [I0]
974 (pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT) // save ar.rnat
975 (pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE) // save ar.bspstore
976 shl r18=r18,16 // compute ar.rsc to be used for "loadrs"
978 st8 [r16]=r31,PT(LOADRS)-PT(PR) // save predicates
979 st8 [r17]=r28,PT(R1)-PT(B0) // save b0
980 tnat.nz p13,p0=in5 // [I0]
982 st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs"
983 st8.spill [r17]=r20,PT(R13)-PT(R1) // save original r1
987 .mem.offset 0,0; st8.spill [r16]=r12,PT(AR_FPSR)-PT(R12) // save r12
988 .mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13) // save r13
991 st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr
993 cmp.lt p10,p9=r11,r8 // frame size can't be more than local+8
996 (p9) tnat.nz p10,p0=r15
997 adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch)
999 st8.spill [r17]=r15 // save r15
1003 mov r13=r2 // establish `current'
1004 movl r1=__gp // establish kernel global pointer
1006 st8 [r16]=r8 // ensure pt_regs.r8 != 0 (see handle_syscall_error)
1010 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
1011 movl r17=FPSR_DEFAULT
1013 mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value
1014 (p10) mov r8=-EINVAL
1016 END(ia64_syscall_setup)
1018 .org ia64_ivt+0x3c00
1019 /////////////////////////////////////////////////////////////////////////////////////////
1020 // 0x3c00 Entry 15 (size 64 bundles) Reserved
1025 * Squatting in this space ...
1027 * This special case dispatcher for illegal operation faults allows preserved
1028 * registers to be modified through a callback function (asm only) that is handed
1029 * back from the fault handler in r8. Up to three arguments can be passed to the
1030 * callback function by returning an aggregate with the callback as its first
1031 * element, followed by the arguments.
1033 ENTRY(dispatch_illegal_op_fault)
1037 ssm psr.ic | PSR_DEFAULT_BITS
1039 srlz.i // guarantee that interruption collection is on
1041 (p15) ssm psr.i // restore psr.i
1042 adds r3=8,r2 // set up second base pointer for SAVE_REST
1044 alloc r14=ar.pfs,0,0,1,0 // must be first in insn group
1048 PT_REGS_UNWIND_INFO(0)
1050 br.call.sptk.many rp=ia64_illegal_op_fault
1052 alloc r14=ar.pfs,0,0,3,0 // must be first in insn group
1056 movl r15=ia64_leave_kernel
1062 (p6) br.call.dpnt.many b6=b6 // call returns to ia64_leave_kernel
1063 br.sptk.many ia64_leave_kernel
1064 END(dispatch_illegal_op_fault)
1066 .org ia64_ivt+0x4000
1067 /////////////////////////////////////////////////////////////////////////////////////////
1068 // 0x4000 Entry 16 (size 64 bundles) Reserved
1072 .org ia64_ivt+0x4400
1073 /////////////////////////////////////////////////////////////////////////////////////////
1074 // 0x4400 Entry 17 (size 64 bundles) Reserved
1079 mov ar.rsc=r27 // restore ar.rsc before SAVE_MIN_WITH_COVER
1083 // There is no particular reason for this code to be here, other than that
1084 // there happens to be space here that would go unused otherwise. If this
1085 // fault ever gets "unreserved", simply moved the following code to a more
1088 alloc r14=ar.pfs,0,0,2,0
1091 adds r3=8,r2 // set up second base pointer for SAVE_REST
1093 ssm psr.ic | PSR_DEFAULT_BITS
1095 srlz.i // guarantee that interruption collection is on
1097 (p15) ssm psr.i // restore psr.i
1098 movl r15=ia64_leave_kernel
1103 br.call.sptk.many b6=ia64_bad_break // avoid WAW on CFM and ignore return addr
1106 .org ia64_ivt+0x4800
1107 /////////////////////////////////////////////////////////////////////////////////////////
1108 // 0x4800 Entry 18 (size 64 bundles) Reserved
1113 * There is no particular reason for this code to be here, other than that
1114 * there happens to be space here that would go unused otherwise. If this
1115 * fault ever gets "unreserved", simply moved the following code to a more
1119 ENTRY(dispatch_unaligned_handler)
1122 alloc r14=ar.pfs,0,0,2,0 // now it's safe (must be first in insn group!)
1126 ssm psr.ic | PSR_DEFAULT_BITS
1128 srlz.i // guarantee that interruption collection is on
1130 (p15) ssm psr.i // restore psr.i
1131 adds r3=8,r2 // set up second base pointer
1134 movl r14=ia64_leave_kernel
1137 br.sptk.many ia64_prepare_handle_unaligned
1138 END(dispatch_unaligned_handler)
1140 .org ia64_ivt+0x4c00
1141 /////////////////////////////////////////////////////////////////////////////////////////
1142 // 0x4c00 Entry 19 (size 64 bundles) Reserved
1147 * There is no particular reason for this code to be here, other than that
1148 * there happens to be space here that would go unused otherwise. If this
1149 * fault ever gets "unreserved", simply moved the following code to a more
1153 ENTRY(dispatch_to_fault_handler)
1157 * r19: fault vector number (e.g., 24 for General Exception)
1158 * r31: contains saved predicates (pr)
1160 SAVE_MIN_WITH_COVER_R19
1161 alloc r14=ar.pfs,0,0,5,0
1168 ssm psr.ic | PSR_DEFAULT_BITS
1170 srlz.i // guarantee that interruption collection is on
1172 (p15) ssm psr.i // restore psr.i
1173 adds r3=8,r2 // set up second base pointer for SAVE_REST
1176 movl r14=ia64_leave_kernel
1179 br.call.sptk.many b6=ia64_fault
1180 END(dispatch_to_fault_handler)
1183 // --- End of long entries, Beginning of short entries
1186 .org ia64_ivt+0x5000
1187 /////////////////////////////////////////////////////////////////////////////////////////
1188 // 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49)
1189 ENTRY(page_not_present)
1194 * The Linux page fault handler doesn't expect non-present pages to be in
1195 * the TLB. Flush the existing entry now, so we meet that expectation.
1197 mov r17=PAGE_SHIFT<<2
1203 br.sptk.many page_fault
1204 END(page_not_present)
1206 .org ia64_ivt+0x5100
1207 /////////////////////////////////////////////////////////////////////////////////////////
1208 // 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52)
1209 ENTRY(key_permission)
1216 br.sptk.many page_fault
1219 .org ia64_ivt+0x5200
1220 /////////////////////////////////////////////////////////////////////////////////////////
1221 // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
1222 ENTRY(iaccess_rights)
1229 br.sptk.many page_fault
1232 .org ia64_ivt+0x5300
1233 /////////////////////////////////////////////////////////////////////////////////////////
1234 // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
1235 ENTRY(daccess_rights)
1242 br.sptk.many page_fault
1245 .org ia64_ivt+0x5400
1246 /////////////////////////////////////////////////////////////////////////////////////////
1247 // 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
1248 ENTRY(general_exception)
1254 (p6) br.sptk.many dispatch_illegal_op_fault
1256 mov r19=24 // fault number
1257 br.sptk.many dispatch_to_fault_handler
1258 END(general_exception)
1260 .org ia64_ivt+0x5500
1261 /////////////////////////////////////////////////////////////////////////////////////////
1262 // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
1263 ENTRY(disabled_fp_reg)
1265 rsm psr.dfh // ensure we can access fph
1270 br.sptk.many dispatch_to_fault_handler
1271 END(disabled_fp_reg)
1273 .org ia64_ivt+0x5600
1274 /////////////////////////////////////////////////////////////////////////////////////////
1275 // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
1276 ENTRY(nat_consumption)
1281 mov r31=pr // save PR
1283 and r18=0xf,r17 // r18 = cr.ipsr.code{3:0}
1284 tbit.z p6,p0=r17,IA64_ISR_NA_BIT
1286 cmp.ne.or p6,p0=IA64_ISR_CODE_LFETCH,r18
1287 dep r16=-1,r16,IA64_PSR_ED_BIT,1
1288 (p6) br.cond.spnt 1f // branch if (cr.ispr.na == 0 || cr.ipsr.code{3:0} != LFETCH)
1290 mov cr.ipsr=r16 // set cr.ipsr.na
1298 END(nat_consumption)
1300 .org ia64_ivt+0x5700
1301 /////////////////////////////////////////////////////////////////////////////////////////
1302 // 0x5700 Entry 27 (size 16 bundles) Speculation (40)
1303 ENTRY(speculation_vector)
1306 * A [f]chk.[as] instruction needs to take the branch to the recovery code but
1307 * this part of the architecture is not implemented in hardware on some CPUs, such
1308 * as Itanium. Thus, in general we need to emulate the behavior. IIM contains
1309 * the relative target (not yet sign extended). So after sign extending it we
1310 * simply add it to IIP. We also need to reset the EI field of the IPSR to zero,
1311 * i.e., the slot to restart into.
1313 * cr.imm contains zero_ext(imm21)
1318 shl r18=r18,43 // put sign bit in position (43=64-21)
1322 shr r18=r18,39 // sign extend (39=43-4)
1325 add r17=r17,r18 // now add the offset
1328 dep r16=0,r16,41,2 // clear EI
1335 END(speculation_vector)
1337 .org ia64_ivt+0x5800
1338 /////////////////////////////////////////////////////////////////////////////////////////
1339 // 0x5800 Entry 28 (size 16 bundles) Reserved
1343 .org ia64_ivt+0x5900
1344 /////////////////////////////////////////////////////////////////////////////////////////
1345 // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
1351 .org ia64_ivt+0x5a00
1352 /////////////////////////////////////////////////////////////////////////////////////////
1353 // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
1354 ENTRY(unaligned_access)
1357 mov r31=pr // prepare to save predicates
1359 br.sptk.many dispatch_unaligned_handler
1360 END(unaligned_access)
1362 .org ia64_ivt+0x5b00
1363 /////////////////////////////////////////////////////////////////////////////////////////
1364 // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
1365 ENTRY(unsupported_data_reference)
1368 END(unsupported_data_reference)
1370 .org ia64_ivt+0x5c00
1371 /////////////////////////////////////////////////////////////////////////////////////////
1372 // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
1373 ENTRY(floating_point_fault)
1376 END(floating_point_fault)
1378 .org ia64_ivt+0x5d00
1379 /////////////////////////////////////////////////////////////////////////////////////////
1380 // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
1381 ENTRY(floating_point_trap)
1384 END(floating_point_trap)
1386 .org ia64_ivt+0x5e00
1387 /////////////////////////////////////////////////////////////////////////////////////////
1388 // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
1389 ENTRY(lower_privilege_trap)
1392 END(lower_privilege_trap)
1394 .org ia64_ivt+0x5f00
1395 /////////////////////////////////////////////////////////////////////////////////////////
1396 // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
1397 ENTRY(taken_branch_trap)
1400 END(taken_branch_trap)
1402 .org ia64_ivt+0x6000
1403 /////////////////////////////////////////////////////////////////////////////////////////
1404 // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
1405 ENTRY(single_step_trap)
1408 END(single_step_trap)
1410 .org ia64_ivt+0x6100
1411 /////////////////////////////////////////////////////////////////////////////////////////
1412 // 0x6100 Entry 37 (size 16 bundles) Reserved
1416 .org ia64_ivt+0x6200
1417 /////////////////////////////////////////////////////////////////////////////////////////
1418 // 0x6200 Entry 38 (size 16 bundles) Reserved
1422 .org ia64_ivt+0x6300
1423 /////////////////////////////////////////////////////////////////////////////////////////
1424 // 0x6300 Entry 39 (size 16 bundles) Reserved
1428 .org ia64_ivt+0x6400
1429 /////////////////////////////////////////////////////////////////////////////////////////
1430 // 0x6400 Entry 40 (size 16 bundles) Reserved
1434 .org ia64_ivt+0x6500
1435 /////////////////////////////////////////////////////////////////////////////////////////
1436 // 0x6500 Entry 41 (size 16 bundles) Reserved
1440 .org ia64_ivt+0x6600
1441 /////////////////////////////////////////////////////////////////////////////////////////
1442 // 0x6600 Entry 42 (size 16 bundles) Reserved
1446 .org ia64_ivt+0x6700
1447 /////////////////////////////////////////////////////////////////////////////////////////
1448 // 0x6700 Entry 43 (size 16 bundles) Reserved
1452 .org ia64_ivt+0x6800
1453 /////////////////////////////////////////////////////////////////////////////////////////
1454 // 0x6800 Entry 44 (size 16 bundles) Reserved
1458 .org ia64_ivt+0x6900
1459 /////////////////////////////////////////////////////////////////////////////////////////
1460 // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77)
1461 ENTRY(ia32_exception)
1466 .org ia64_ivt+0x6a00
1467 /////////////////////////////////////////////////////////////////////////////////////////
1468 // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71)
1469 ENTRY(ia32_intercept)
1471 #ifdef CONFIG_IA32_SUPPORT
1475 extr.u r17=r16,16,8 // get ISR.code
1477 mov r19=cr.iim // old eflag value
1480 (p6) br.cond.spnt 1f // not a system flag fault
1483 extr.u r17=r16,18,1 // get the eflags.ac bit
1486 (p6) br.cond.spnt 1f // eflags.ac bit didn't change
1488 mov pr=r31,-1 // restore predicate registers
1492 #endif // CONFIG_IA32_SUPPORT
1496 .org ia64_ivt+0x6b00
1497 /////////////////////////////////////////////////////////////////////////////////////////
1498 // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74)
1499 ENTRY(ia32_interrupt)
1501 #ifdef CONFIG_IA32_SUPPORT
1503 br.sptk.many dispatch_to_ia32_handler
1509 .org ia64_ivt+0x6c00
1510 /////////////////////////////////////////////////////////////////////////////////////////
1511 // 0x6c00 Entry 48 (size 16 bundles) Reserved
1515 .org ia64_ivt+0x6d00
1516 /////////////////////////////////////////////////////////////////////////////////////////
1517 // 0x6d00 Entry 49 (size 16 bundles) Reserved
1521 .org ia64_ivt+0x6e00
1522 /////////////////////////////////////////////////////////////////////////////////////////
1523 // 0x6e00 Entry 50 (size 16 bundles) Reserved
1527 .org ia64_ivt+0x6f00
1528 /////////////////////////////////////////////////////////////////////////////////////////
1529 // 0x6f00 Entry 51 (size 16 bundles) Reserved
1533 .org ia64_ivt+0x7000
1534 /////////////////////////////////////////////////////////////////////////////////////////
1535 // 0x7000 Entry 52 (size 16 bundles) Reserved
1539 .org ia64_ivt+0x7100
1540 /////////////////////////////////////////////////////////////////////////////////////////
1541 // 0x7100 Entry 53 (size 16 bundles) Reserved
1545 .org ia64_ivt+0x7200
1546 /////////////////////////////////////////////////////////////////////////////////////////
1547 // 0x7200 Entry 54 (size 16 bundles) Reserved
1551 .org ia64_ivt+0x7300
1552 /////////////////////////////////////////////////////////////////////////////////////////
1553 // 0x7300 Entry 55 (size 16 bundles) Reserved
1557 .org ia64_ivt+0x7400
1558 /////////////////////////////////////////////////////////////////////////////////////////
1559 // 0x7400 Entry 56 (size 16 bundles) Reserved
1563 .org ia64_ivt+0x7500
1564 /////////////////////////////////////////////////////////////////////////////////////////
1565 // 0x7500 Entry 57 (size 16 bundles) Reserved
1569 .org ia64_ivt+0x7600
1570 /////////////////////////////////////////////////////////////////////////////////////////
1571 // 0x7600 Entry 58 (size 16 bundles) Reserved
1575 .org ia64_ivt+0x7700
1576 /////////////////////////////////////////////////////////////////////////////////////////
1577 // 0x7700 Entry 59 (size 16 bundles) Reserved
1581 .org ia64_ivt+0x7800
1582 /////////////////////////////////////////////////////////////////////////////////////////
1583 // 0x7800 Entry 60 (size 16 bundles) Reserved
1587 .org ia64_ivt+0x7900
1588 /////////////////////////////////////////////////////////////////////////////////////////
1589 // 0x7900 Entry 61 (size 16 bundles) Reserved
1593 .org ia64_ivt+0x7a00
1594 /////////////////////////////////////////////////////////////////////////////////////////
1595 // 0x7a00 Entry 62 (size 16 bundles) Reserved
1599 .org ia64_ivt+0x7b00
1600 /////////////////////////////////////////////////////////////////////////////////////////
1601 // 0x7b00 Entry 63 (size 16 bundles) Reserved
1605 .org ia64_ivt+0x7c00
1606 /////////////////////////////////////////////////////////////////////////////////////////
1607 // 0x7c00 Entry 64 (size 16 bundles) Reserved
1611 .org ia64_ivt+0x7d00
1612 /////////////////////////////////////////////////////////////////////////////////////////
1613 // 0x7d00 Entry 65 (size 16 bundles) Reserved
1617 .org ia64_ivt+0x7e00
1618 /////////////////////////////////////////////////////////////////////////////////////////
1619 // 0x7e00 Entry 66 (size 16 bundles) Reserved
1623 .org ia64_ivt+0x7f00
1624 /////////////////////////////////////////////////////////////////////////////////////////
1625 // 0x7f00 Entry 67 (size 16 bundles) Reserved
1629 #ifdef CONFIG_IA32_SUPPORT
1632 * There is no particular reason for this code to be here, other than that
1633 * there happens to be space here that would go unused otherwise. If this
1634 * fault ever gets "unreserved", simply moved the following code to a more
1638 // IA32 interrupt entry point
1640 ENTRY(dispatch_to_ia32_handler)
1644 ssm psr.ic | PSR_DEFAULT_BITS
1646 srlz.i // guarantee that interruption collection is on
1649 adds r3=8,r2 // Base pointer for SAVE_REST
1654 shr r14=r14,16 // Get interrupt number
1656 cmp.ne p6,p0=r14,r15
1657 (p6) br.call.dpnt.many b6=non_ia32_syscall
1659 adds r14=IA64_PT_REGS_R8_OFFSET + 16,sp // 16 byte hole per SW conventions
1660 adds r15=IA64_PT_REGS_R1_OFFSET + 16,sp
1662 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
1663 ld8 r8=[r14] // get r8
1665 st8 [r15]=r8 // save original EAX in r1 (IA32 procs don't use the GP)
1667 alloc r15=ar.pfs,0,0,6,0 // must first in an insn group
1669 ld4 r8=[r14],8 // r8 == eax (syscall number)
1670 mov r15=IA32_NR_syscalls
1672 cmp.ltu.unc p6,p7=r8,r15
1673 ld4 out1=[r14],8 // r9 == ecx
1675 ld4 out2=[r14],8 // r10 == edx
1677 ld4 out0=[r14] // r11 == ebx
1678 adds r14=(IA64_PT_REGS_R13_OFFSET) + 16,sp
1680 ld4 out5=[r14],PT(R14)-PT(R13) // r13 == ebp
1682 ld4 out3=[r14],PT(R15)-PT(R14) // r14 == esi
1683 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
1685 ld4 out4=[r14] // r15 == edi
1686 movl r16=ia32_syscall_table
1688 (p6) shladd r16=r8,3,r16 // force ni_syscall if not valid syscall number
1689 ld4 r2=[r2] // r2 = current_thread_info()->flags
1692 and r2=_TIF_SYSCALL_TRACEAUDIT,r2 // mask trace or audit
1695 movl r15=ia32_ret_from_syscall
1699 (p8) br.call.sptk.many b6=b6
1700 br.cond.sptk ia32_trace_syscall
1703 alloc r15=ar.pfs,0,0,2,0
1704 mov out0=r14 // interrupt #
1705 add out1=16,sp // pointer to pt_regs
1706 ;; // avoid WAW on CFM
1707 br.call.sptk.many rp=ia32_bad_interrupt
1708 .ret1: movl r15=ia64_leave_kernel
1712 END(dispatch_to_ia32_handler)
1714 #endif /* CONFIG_IA32_SUPPORT */