2 * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
3 * Copyright (C) 2004 Intel Corp.
5 * This code is released under the GNU General Public License version 2.
9 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
12 #include <linux/pci.h>
13 #include <linux/init.h>
14 #include <linux/acpi.h>
18 /* Assume systems with more busses have correct MCFG */
19 #define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
21 /* The base address of the last MMCONFIG device accessed */
22 static u32 mmcfg_last_accessed_device;
23 static int mmcfg_last_accessed_cpu;
26 * Functions for accessing PCI configuration space with MMCONFIG accesses
28 static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
31 struct acpi_mcfg_allocation *cfg;
33 if (seg == 0 && bus < PCI_MMCFG_MAX_CHECK_BUS &&
34 test_bit(PCI_SLOT(devfn) + 32*bus, pci_mmcfg_fallback_slots))
39 if (cfg_num >= pci_mmcfg_config_num) {
42 cfg = &pci_mmcfg_config[cfg_num];
43 if (cfg->pci_segment != seg)
45 if ((cfg->start_bus_number <= bus) &&
46 (cfg->end_bus_number >= bus))
50 /* Handle more broken MCFG tables on Asus etc.
51 They only contain a single entry for bus 0-0. Assume
52 this applies to all busses. */
53 cfg = &pci_mmcfg_config[0];
54 if (pci_mmcfg_config_num == 1 &&
55 cfg->pci_segment == 0 &&
56 (cfg->start_bus_number | cfg->end_bus_number) == 0)
59 /* Fall back to type 0 */
64 * This is always called under pci_config_lock
66 static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
68 u32 dev_base = base | (bus << 20) | (devfn << 12);
69 int cpu = smp_processor_id();
70 if (dev_base != mmcfg_last_accessed_device ||
71 cpu != mmcfg_last_accessed_cpu) {
72 mmcfg_last_accessed_device = dev_base;
73 mmcfg_last_accessed_cpu = cpu;
74 set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
78 static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
79 unsigned int devfn, int reg, int len, u32 *value)
84 if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
89 base = get_base_addr(seg, bus, devfn);
91 return pci_conf1_read(seg,bus,devfn,reg,len,value);
93 spin_lock_irqsave(&pci_config_lock, flags);
95 pci_exp_set_dev_base(base, bus, devfn);
99 *value = readb(mmcfg_virt_addr + reg);
102 *value = readw(mmcfg_virt_addr + reg);
105 *value = readl(mmcfg_virt_addr + reg);
109 spin_unlock_irqrestore(&pci_config_lock, flags);
114 static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
115 unsigned int devfn, int reg, int len, u32 value)
120 if ((bus > 255) || (devfn > 255) || (reg > 4095))
123 base = get_base_addr(seg, bus, devfn);
125 return pci_conf1_write(seg,bus,devfn,reg,len,value);
127 spin_lock_irqsave(&pci_config_lock, flags);
129 pci_exp_set_dev_base(base, bus, devfn);
133 writeb(value, mmcfg_virt_addr + reg);
136 writew(value, mmcfg_virt_addr + reg);
139 writel(value, mmcfg_virt_addr + reg);
143 spin_unlock_irqrestore(&pci_config_lock, flags);
148 static struct pci_raw_ops pci_mmcfg = {
149 .read = pci_mmcfg_read,
150 .write = pci_mmcfg_write,
153 int __init pci_mmcfg_arch_init(void)
155 printk(KERN_INFO "PCI: Using MMCONFIG\n");
156 raw_pci_ops = &pci_mmcfg;